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MC74LCX16500DTR2 PDF预览

MC74LCX16500DTR2

更新时间: 2024-11-04 15:43:51
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
21页 540K
描述
IC LVC/LCX/Z SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-56, Bus Driver/Transceiver

MC74LCX16500DTR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP,
针数:56Reach Compliance Code:compliant
风险等级:5.63系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G56JESD-609代码:e0
长度:14 mm逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
位数:18功能数量:1
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):225传播延迟(tpd):8 ns
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.1 mm
Base Number Matches:1

MC74LCX16500DTR2 数据手册

 浏览型号MC74LCX16500DTR2的Datasheet PDF文件第2页浏览型号MC74LCX16500DTR2的Datasheet PDF文件第3页浏览型号MC74LCX16500DTR2的Datasheet PDF文件第4页浏览型号MC74LCX16500DTR2的Datasheet PDF文件第5页浏览型号MC74LCX16500DTR2的Datasheet PDF文件第6页浏览型号MC74LCX16500DTR2的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
The MC74LCX16500 is a high performance, non–inverting 18–bit  
universal bus transceiver operating from a 2.7 to 3.6V supply. This part is  
not byte controlled; it is “18–bit” controlled. High impedance TTL  
compatible inputs significantly reduce current loading to input drivers  
while TTL compatible outputs offer improved switching noise  
LOW–VOLTAGE CMOS  
18–BIT UNIVERSAL BUS  
TRANSCEIVER  
performance. A V specification of 5.5V allows MC74LCX16500 inputs to  
I
be safely driven from 5V devices. The MC74LCX16500 is suitable for  
memory address driving and all TTL level bus oriented transceiver  
applications.  
Data flow in each direction is controlled by Output Enable (OEAB,  
OEBA), Latch Enable (LEAB, LEBA) and Clock inputs (CAB, CBA). When  
LEAB is HIGH, the A–to–B dataflow is transparent. When LEAB is LOW,  
and CAB is held at LOW or HIGH, the data A is latched; on the  
HIGH–to–LOW transition of CAB the A–data is stored in the  
latch/flip–flop. The outputs are active when OEAB is HIGH. When OEAB  
is LOW the B–outputs are in 3–state. Similarly, the LEBA, OEBA and CBA  
control the B–to–A dataflow. Please note that the output enables are  
complementary; OEAB is active HIGH, OEBA is active LOW.  
DT SUFFIX  
PLASTIC TSSOP PACKAGE  
CASE 1202–01  
Designed for 2.7 to 3.6V V  
CC  
Operation  
6ns Maximum t  
pd  
5V Tolerant — Interface Capability With 5V TTL Logic  
Supports Live Insertion and Withdrawal  
I  
OFF  
Specification Guarantees High Impedance When V  
= 0V  
CC  
LVTTL Compatible  
LVCMOS Compatible  
PIN NAMES  
24mA Balanced Output Sink and Source Capability  
Near Zero Static Supply Current in All Three Logic States (20µA)  
Pins  
Function  
Substantially Reduces System Power Requirements  
OEAB, OEBA  
CAB, CBA  
LEAB, LEBA  
A0–A17  
Output Enable Inputs  
Clock Pulse Inputs  
Latch Enable Inputs  
Side A Inputs/Outputs  
Side B Inputs/Outputs  
Latchup Performance Exceeds 500mA  
ESD Performance: Human Body Model >2000V; Machine  
Model >200V  
B0–B17  
This document contains information on a new product. Specifications and information herein are subject to  
change without notice.  
11/96  
REV 0.2  
181  
Motorola, Inc. 1996  

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