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MC74LCX16500DT PDF预览

MC74LCX16500DT

更新时间： 2024-11-03 23:05:47
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
10页 165K
描述
LOW-VOLTAGE CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER

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中文翻译

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MC74LCX16500DT 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP56,.3,20
针数：56Reach Compliance Code：unknown
风险等级：5.63Is Samacsys：N
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G56JESD-609代码：e0
长度：14 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.024 A位数：18
功能数量：1端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP56,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
Prop。Delay @ Nom-Sup：6 ns传播延迟（tpd）：8 ns
认证状态：Not Qualified座面最大高度：1.1 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：NEGATIVE EDGE宽度：6.1 mm
Base Number Matches：1

MC74LCX16500DT 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74LCX16500 is a high performance, non–inverting 18–bit  
universal bus transceiver operating from a 2.7 to 3.6V supply. This part is  
not byte controlled; it is “18–bit” controlled. High impedance TTL  
compatible inputs significantly reduce current loading to input drivers  
while TTL compatible outputs offer improved switching noise  
LOW–VOLTAGE CMOS  
18–BIT UNIVERSAL BUS  
TRANSCEIVER  
performance. A V specification of 5.5V allows MC74LCX16500 inputs to  
I
be safely driven from 5V devices. The MC74LCX16500 is suitable for  
memory address driving and all TTL level bus oriented transceiver  
applications.  
Data flow in each direction is controlled by Output Enable (OEAB,  
OEBA), Latch Enable (LEAB, LEBA) and Clock inputs (CAB, CBA). When  
LEAB is HIGH, the A–to–B dataflow is transparent. When LEAB is LOW,  
and CAB is held at LOW or HIGH, the data A is latched; on the  
HIGH–to–LOW transition of CAB the A–data is stored in the  
latch/flip–flop. The outputs are active when OEAB is HIGH. When OEAB  
is LOW the B–outputs are in 3–state. Similarly, the LEBA, OEBA and CBA  
control the B–to–A dataflow. Please note that the output enables are  
complementary; OEAB is active HIGH, OEBA is active LOW.  
DT SUFFIX  
56–LEAD PLASTIC TSSOP PACKAGE  
CASE 1202–01  
• Designed for 2.7 to 3.6V V  
CC  
Operation  
• 6ns Maximum t  
pd  
• 5V Tolerant — Interface Capability With 5V TTL Logic  
• Supports Live Insertion and Withdrawal  
• I  
OFF  
Specification Guarantees High Impedance When V  
= 0V  
CC  
• LVTTL Compatible  
• LVCMOS Compatible  
PIN NAMES  
• 24mA Balanced Output Sink and Source Capability  
Pins  
Function  
• Near Zero Static Supply Current in All Three Logic States (20µA)  
Substantially Reduces System Power Requirements  
OEAB, OEBA  
CAB, CBA  
LEAB, LEBA  
A0–A17  
Output Enable Inputs  
Clock Pulse Inputs  
Latch Enable Inputs  
Side A Inputs/Outputs  
Side B Inputs/Outputs  
• Latchup Performance Exceeds 500mA  
• ESD Performance: Human Body Model >2000V; Machine  
Model >200V  
B0–B17  
3/97  
REV 1  
Motorola, Inc. 1997  
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MC74LCX16500DTR2 MOTOROLA

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 		LOW-VOLTAGE CMOS 16-BIT LATCHING TRANSCEIVER
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MC74LCX16543ADT ONSEMI

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 		LVC/LCX/Z SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-5
MC74LCX16543ADTR MOTOROLA

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 		LVC/LCX/Z SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-5

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