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MC74LCX16373DT PDF预览

MC74LCX16373DT

更新时间: 2024-02-22 16:54:51
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 99K
描述
Low−Voltage CMOS 16−Bit Transparent Latch With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting)

MC74LCX16373DT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP48,.3,20
针数:48Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.15
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G48
JESD-609代码:e4长度:12.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:8功能数量:2
端口数量:2端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP48,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:5.4 ns传播延迟(tpd):6.6 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:FF/Latches最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:6.1 mmBase Number Matches:1

MC74LCX16373DT 数据手册

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MC74LCX16373  
Low−Voltage CMOS 16−Bit  
Transparent Latch  
With 5 V−Tolerant Inputs and Outputs  
(3−State, Non−Inverting)  
http://onsemi.com  
The MC74LCX16373 is a high performance, non−inverting 16−bit  
transparent latch operating from a 2.3 V to 3.6 V supply. The device is  
byte controlled. Each byte has separate Output Enable and Latch Enable  
inputs. These control pins can be tied together for full 16−bit operation.  
High impedance TTL compatible inputs significantly reduce current  
loading to input drivers while TTL compatible outputs offer improved  
TSSOP−48  
DT SUFFIX  
CASE 1201  
48  
switching noise performance. A V specification of 5.5 V allows  
I
1
MC74LCX16373 inputs to be safely driven from 5.0 V devices.  
The MC74LCX16373 contains 16 D−type latches with 3−state  
5.0 V−tolerant outputs. When the Latch Enable (LEn) inputs are HIGH,  
data on the Dn inputs enters the latches. In this condition, the latches are  
transparent, i.e., a latch output will change state each time its D input  
changes. When LE is LOW, the latches store the information that was  
present on the D inputs a setup time preceding the HIGH−to−LOW  
transition of LE. The 3−state outputs are controlled by the Output  
Enable (OEn) inputs. When OE is LOW, the outputs are enabled. When  
OE is HIGH, the standard outputs are in the high impedance state, but  
this does not interfere with new data entering into the latches.  
MARKING DIAGRAM  
48  
LCX16373G  
AWLYYWW  
Features  
Designed for 2.3 to 3.6 V V Operation  
CC  
5.4 ns Maximum t  
pd  
1
5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic  
Supports Live Insertion and Withdrawal  
A
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
I  
Specification Guarantees High Impedance When V = 0 V  
CC  
OFF  
WL  
YY  
WW  
G
LVTTL Compatible  
LVCMOS Compatible  
24 mA Balanced Output Sink and Source Capability  
Near Zero Static Supply Current in All Three Logic States (20 mA)  
Substantially Reduces System Power Requirements  
Latchup Performance Exceeds 500 mA  
ESD Performance: Human Body Model >2000 V;  
Machine Model >200 V  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
These are Pb−Free Devices*  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
© Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
August, 2005 − Rev. 6  
MC74LCX16373/D  

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