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MC74LCX16245DTG PDF预览

MC74LCX16245DTG

更新时间: 2024-01-22 19:06:35
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 95K
描述
Low−Voltage CMOS 16−Bit Transceiver With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting)

MC74LCX16245DTG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:48
Reach Compliance Code:unknown风险等级:5.71
其他特性:WITH DIRECTION CONTROL系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G48JESD-609代码:e4
长度:12.5 mm逻辑集成电路类型:BUS TRANSCEIVER
湿度敏感等级:NOT SPECIFIED位数:8
功能数量:2端口数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
传播延迟(tpd):5.4 ns认证状态:COMMERCIAL
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:6.1 mm

MC74LCX16245DTG 数据手册

 浏览型号MC74LCX16245DTG的Datasheet PDF文件第2页浏览型号MC74LCX16245DTG的Datasheet PDF文件第3页浏览型号MC74LCX16245DTG的Datasheet PDF文件第4页浏览型号MC74LCX16245DTG的Datasheet PDF文件第5页浏览型号MC74LCX16245DTG的Datasheet PDF文件第6页浏览型号MC74LCX16245DTG的Datasheet PDF文件第7页 
MC74LCX16245  
Low−Voltage CMOS  
16−Bit Transceiver  
With 5 V−Tolerant Inputs and Outputs  
(3−State, Non−Inverting)  
http://onsemi.com  
The MC74LCX16245 is a high performance, non−inverting 16−bit  
transceiver operating from a 2.3 to 3.6 V supply. The device is byte  
controlled. Each byte has separate Output Enable inputs which can be  
tied together for full 16−bit operation. High impedance TTL  
compatible inputs significantly reduce current loading to input drivers  
while TTL compatible outputs offer improved switching noise  
TSSOP−48  
DT SUFFIX  
CASE 1201  
48  
performance. A V specification of 5.5 V allows MC74LCX16245  
I
inputs to be safely driven from 5.0 V devices. The MC74LCX16245 is  
suitable for memory address driving and all TTL level bus oriented  
transceiver applications.  
1
The 4.5 ns maximum propagation delays support high performance  
applications. Current drive capability is 24 mA at both A and B ports.  
The Transmit/Receive (T/Rn) inputs determine the direction of data  
flow through the bidirectional transceiver. Transmit (active−HIGH)  
enables data from A ports to B ports; Receive (active−LOW) enables  
data from B to A ports. The Output Enable inputs (OEn), when HIGH,  
disable both A and B ports by placing them in a HIGH Z condition.  
MARKING DIAGRAM  
48  
Features  
Designed for 2.3 to 3.6 V V Operation  
LCX16245G  
AWLYYWW  
CC  
4.5 ns Maximum t  
pd  
5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic  
Supports Live Insertion and Withdrawal  
1
I  
Specification Guarantees High Impedance When V = 0 V  
CC  
OFF  
LVTTL Compatible  
LVCMOS Compatible  
24 mA Balanced Output Sink and Source Capability  
A
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
WL  
YY  
WW  
G
Near Zero Static Supply Current in All Three Logic States (20 mA)  
Substantially Reduces System Power Requirements  
Latchup Performance Exceeds 500 mA  
ESD Performance: Human Body Model >2000 V;  
Machine Model >200 V  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
These are Pb−Free Devices*  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
© Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
August, 2005 − Rev. 7  
MC74LCX16245/D  

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