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MC74LCX16244DTR2 PDF预览

MC74LCX16244DTR2

更新时间: 2024-11-04 05:22:11
品牌 Logo 应用领域
安森美 - ONSEMI 逻辑集成电路光电二极管驱动
页数 文件大小 规格书
8页 93K
描述
Low−Voltage CMOS 16−Bit Buffer With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting)

MC74LCX16244DTR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP48,.3,20
针数:48Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:7.17控制类型:ENABLE LOW
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G48
JESD-609代码:e0长度:12.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:4功能数量:4
端口数量:2端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP48,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):240电源:3.3 V
Prop。Delay @ Nom-Sup:4.5 ns传播延迟(tpd):5.4 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:6.1 mmBase Number Matches:1

MC74LCX16244DTR2 数据手册

 浏览型号MC74LCX16244DTR2的Datasheet PDF文件第2页浏览型号MC74LCX16244DTR2的Datasheet PDF文件第3页浏览型号MC74LCX16244DTR2的Datasheet PDF文件第4页浏览型号MC74LCX16244DTR2的Datasheet PDF文件第5页浏览型号MC74LCX16244DTR2的Datasheet PDF文件第6页浏览型号MC74LCX16244DTR2的Datasheet PDF文件第7页 
MC74LCX16244  
Low−Voltage CMOS  
16−Bit Buffer  
With 5 V−Tolerant Inputs and Outputs  
(3−State, Non−Inverting)  
http://onsemi.com  
The MC74LCX16244 is a high performance, non−inverting 16−bit  
buffer operating from a 2.3 to 3.6 V supply. The device is nibble  
controlled. Each nibble has separate Output Enable inputs which can  
be tied together for full 16−bit operation. High impedance TTL  
compatible inputs significantly reduce current loading to input drivers  
while TTL compatible outputs offer improved switching noise  
TSSOP−48  
DT SUFFIX  
CASE 1201  
48  
performance. A V specification of 5.5 V allows MC74LCX16244  
I
1
inputs to be safely driven from 5.0 V devices. The MC74LCX16244 is  
suitable for memory address driving and all TTL level bus oriented  
transceiver applications.  
The 4.5 ns maximum propagation delays support high performance  
applications. Current drive capability is 24 mA at the outputs. The  
Output Enable (OEn) inputs, when HIGH, disable the outputs by  
placing them in a HIGH Z condition.  
MARKING DIAGRAM  
The MC74LCX16244 contains sixteen non−inverting buffers with  
3−state 5.0 V−tolerant outputs. The device is nibble controlled with  
each nibble functioning identically, but independently. The control  
pins may be tied together to obtain full 16−bit operation. The 3−state  
outputs are controlled by an Output Enable (OEn) input for each  
nibble. When OEn is LOW, the outputs are on. When OEn is HIGH,  
the outputs are in the high impedance state.  
48  
LCX16244G  
AWLYYWW  
Features  
1
Designed for 2.3 V to 3.6 V V Operation  
CC  
4.5 ns Maximum t  
pd  
5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic  
Supports Live Insertion and Withdrawal  
A
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
WL  
YY  
WW  
G
I  
Specification Guarantees High Impedance When V = 0 V  
CC  
OFF  
LVTTL Compatible  
LVCMOS Compatible  
24 mA Balanced Output Sink and Source Capability  
Near Zero Static Supply Current in All Three Logic States (20 mA)  
Substantially Reduces System Power Requirements  
Latchup Performance Exceeds 500 mA  
ESD Performance: Human Body Model >2000 V;  
Machine Model >200 V  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
These are Pb−Free Devices*  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
© Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
August, 2005 − Rev. 6  
MC74LCX16244/D  

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