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MC74LCX05M PDF预览

MC74LCX05M

更新时间: 2024-11-03 23:05:47
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 栅极逻辑集成电路光电二极管
页数 文件大小 规格书
4页 119K
描述
LOW-VOLTAGE CMOS HEX INVERTER OPEN DRAIN

MC74LCX05M 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.74Is Samacsys:N
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G14
长度:10.2 mm逻辑集成电路类型:INVERTER
功能数量:6输入次数:1
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出特性:OPEN-DRAIN
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
认证状态:Not Qualified座面最大高度:2.05 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:5.275 mm
Base Number Matches:1

MC74LCX05M 数据手册

 浏览型号MC74LCX05M的Datasheet PDF文件第2页浏览型号MC74LCX05M的Datasheet PDF文件第3页浏览型号MC74LCX05M的Datasheet PDF文件第4页 
SEMICONDUCTOR TECHNICAL DATA  
The MC74LCX05 is a high performance open drain hex inverter  
operating from a 2.7 to 3.6V supply. High impedance TTL compatible  
inputs significantly reduce current loading to input drivers. A V  
specification of 5.5V allows MC74LCX05 inputs to be safely driven from  
5V devices.  
I
LOW–VOLTAGE CMOS  
HEX INVERTER  
The MC74LCX05 requires the addition of an external resistor to  
perform a wire–NOR function. The open drain output with a 5V pull–up  
resistor can be utlilized to drive 5V CMOS inputs. Current drive capability  
is 24mA at the outputs.  
OPEN DRAIN  
Designed for 2.7 to 3.6V V  
CC  
Operation  
D SUFFIX  
5V Tolerant Inputs — Interface Capability With 5V TTL Logic  
LVTTL Compatible  
PLASTIC SOIC  
CASE 751A–03  
14  
1
LVCMOS Compatible  
24mA Output Sink Capability  
M SUFFIX  
PLASTIC SOIC EIAJ  
CASE 965–01  
Near Zero Static Supply Current (10µA) Substantially Reduces System  
Power Requirements  
14  
1
Latchup Performance Exceeds 500mA  
ESD Performance: Human Body Model >2000V; Machine Model >200V  
SD SUFFIX  
PLASTIC SSOP  
CASE 940A–03  
V
A3  
13  
O3  
12  
A4  
11  
O4  
10  
A5  
9
O5  
8
CC  
14  
14  
14  
1
1
Pinout: 14–Lead  
(Top View)  
DT SUFFIX  
PLASTIC TSSOP  
CASE 948G–01  
1
2
3
4
5
6
7
A0  
O0  
A1  
O1  
A2  
O2  
GND  
PIN NAMES  
Pins  
LOGIC DIAGRAM  
Function  
1
2
A0  
O0  
O1  
O2  
O3  
O4  
O5  
An  
On  
Data Inputs  
Outputs  
3
4
6
A1  
A2  
A3  
A4  
A5  
5
FUNCTION TABLE  
An  
On  
13  
11  
9
12  
10  
8
L
H
H
L
This document contains information on a product under development. Motorola reserves the right to change or  
discontinue this product without notice.  
9/95  
REV 0  
1
Motorola, Inc. 1996  

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