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MC74LCX02SD PDF预览

MC74LCX02SD

更新时间: 2024-11-24 22:35:31
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 输入元件
页数 文件大小 规格书
7页 139K
描述
LOW-VOLTAGE CMOS QUAD 2-INPUT NOR GATE

MC74LCX02SD 技术参数

生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP14,.3针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.65系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
长度:6.2 mm负载电容(CL):50 pF
逻辑集成电路类型:NOR GATE最大I(ol):0.024 A
功能数量:4输入次数:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP14,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
电源:3.3 VProp。Delay @ Nom-Sup:5.2 ns
传播延迟(tpd):6 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:2 mm
子类别:Gates最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:5.3 mm
Base Number Matches:1

MC74LCX02SD 数据手册

 浏览型号MC74LCX02SD的Datasheet PDF文件第2页浏览型号MC74LCX02SD的Datasheet PDF文件第3页浏览型号MC74LCX02SD的Datasheet PDF文件第4页浏览型号MC74LCX02SD的Datasheet PDF文件第5页浏览型号MC74LCX02SD的Datasheet PDF文件第6页浏览型号MC74LCX02SD的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
The MC74LCX02 is a high performance, quad 2–input NOR gate  
operating from a 2.7 to 3.6V supply. High impedance TTL compatible  
inputs significantly reduce current loading to input drivers while TTL  
compatible outputs offer improved switching noise performance. A V  
specification of 5.5V allows MC74LCX02 inputs to be safely driven from  
5V devices.  
I
LOW–VOLTAGE CMOS  
QUAD 2–INPUT NOR GATE  
Current drive capability is 24mA at the outputs.  
Designed for 2.7 to 3.6V V  
CC  
Operation  
5V Tolerant Inputs — Interface Capability With 5V TTL Logic  
LVTTL Compatible  
D SUFFIX  
PLASTIC SOIC  
CASE 751A–03  
LVCMOS Compatible  
14  
24mA Balanced Output Sink and Source Capability  
1
Near Zero Static Supply Current (10µA) Substantially Reduces System  
Power Requirements  
Latchup Performance Exceeds 500mA  
M SUFFIX  
PLASTIC SOIC EIAJ  
ESD Performance: Human Body Model >2000V; Machine Model >200V  
14  
CASE 965–01  
1
Pinout: 14–Lead (Top View)  
V
O2  
13  
B2  
12  
A2  
11  
O3  
10  
B3  
9
A3  
8
CC  
SD SUFFIX  
PLASTIC SSOP  
14  
14  
CASE 940A–03  
1
DT SUFFIX  
PLASTIC TSSOP  
14  
CASE 948G–01  
1
1
2
3
4
5
6
7
O0  
A0  
B0  
O1  
A1  
B1  
GND  
PIN NAMES  
LOGIC DIAGRAM  
2
Pins  
Function  
A0  
1
O0  
O1  
O2  
O3  
An, Bn  
On  
Data Inputs  
Outputs  
3
5
B0  
A1  
4
13  
10  
6
B1  
A2  
FUNCTION TABLE  
INPUTS  
11  
OUTPUTS  
On  
12  
8
B2  
A3  
An  
Bn  
L
L
L
H
L
H
L
L
L
9
B3  
H
H
H
11/96  
Motorola, Inc. 1996  
REV 1  
1

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