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MC74HCU04ADTEL PDF预览

MC74HCU04ADTEL

更新时间: 2024-11-03 13:02:43
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
8页 162K
描述
IC,LOGIC GATE,HEX INVERTER,HC-CMOS,TSSOP,14PIN,PLASTIC

MC74HCU04ADTEL 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:TSSOP, TSSOP14,.25Reach Compliance Code:not_compliant
风险等级:5.92JESD-30 代码:R-PDSO-G14
JESD-609代码:e0负载电容(CL):50 pF
逻辑集成电路类型:INVERTER最大I(ol):0.0024 A
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL电源:2/6 V
Prop。Delay @ Nom-Sup:50 ns认证状态:Not Qualified
施密特触发器:NO子类别:Gates
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUALBase Number Matches:1

MC74HCU04ADTEL 数据手册

 浏览型号MC74HCU04ADTEL的Datasheet PDF文件第2页浏览型号MC74HCU04ADTEL的Datasheet PDF文件第3页浏览型号MC74HCU04ADTEL的Datasheet PDF文件第4页浏览型号MC74HCU04ADTEL的Datasheet PDF文件第5页浏览型号MC74HCU04ADTEL的Datasheet PDF文件第6页浏览型号MC74HCU04ADTEL的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74HCU04A is identical in pinout to the LS04 and the  
MC14069UB. The device inputs are compatible with standard CMOS  
outputs; with pullup resistors, they are compatible with LSTTL  
outputs.  
http://onsemi.com  
This device consists of six single–stage inverters. These inverters  
are well suited for use as oscillators, pulse shapers, and in many other  
applications requiring a high–input impedance amplifier. For digital  
applications, the HC04A is recommended.  
MARKING  
DIAGRAMS  
14  
PDIP–14  
N SUFFIX  
CASE 646  
MC74HCU04AN  
AWLYYWW  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
1
Operating Voltage Range: 2 to 6 V; 2.5 to 6 V in Oscillator  
Configurations  
14  
SOIC–14  
D SUFFIX  
CASE 751A  
HCU04A  
AWLYWW  
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
1
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
14  
HCU  
04A  
ALYW  
TSSOP–14  
DT SUFFIX  
CASE 948G  
Chip Complexity: 12 FETs or 3 Equivalent Gates  
LOGIC DIAGRAM  
1
A
= Assembly Location  
1
3
5
2
4
6
A1  
A2  
A3  
Y1  
Y2  
Y3  
WL or L = Wafer Lot  
YY or Y = Year  
WW or W = Work Week  
PIN ASSIGNMENT  
A1  
Y1  
1
2
14  
13 A6  
12  
V
CC  
Y = A  
9
8
10  
12  
A4  
A5  
A6  
Y4  
Y5  
Y6  
A2  
Y2  
3
4
Y6  
11 A5  
10 Y5  
11  
13  
A3  
Y3  
5
6
7
PIN 14 = V  
PIN 7 = GND  
CC  
9
8
A4  
Y4  
GND  
FUNCTION TABLE  
Inputs  
A
Outputs  
Y
ORDERING INFORMATION  
L
H
H
L
Device  
Package  
PDIP–14  
Shipping  
MC74HCU04AN  
2000 / Box  
55 / Rail  
MC74HCU04AD  
SOIC–14  
SOIC–14  
TSSOP–14  
TSSOP–14  
MC74HCU04ADR2  
MC74HCU04ADT  
MC74HCU04ADTR2  
2500 / Reel  
96 / Rail  
2500 / Reel  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 2  
MC74HCU04A/D  

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