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MC74HCT373ANG PDF预览

MC74HCT373ANG

更新时间: 2024-11-21 12:48:51
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 153K
描述
Octal 3-State Noninverting Transparent Latch with LSTTL-Compatible Inputs

MC74HCT373ANG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:DIP
包装说明:PLASTIC, DIP-20针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.15Is Samacsys:N
系列:HCTJESD-30 代码:R-PDIP-T20
JESD-609代码:e3长度:26.415 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.006 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):260电源:5 V
Prop。Delay @ Nom-Sup:42 ns传播延迟(tpd):48 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Matte Tin (Sn) - annealed
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:7.62 mmBase Number Matches:1

MC74HCT373ANG 数据手册

 浏览型号MC74HCT373ANG的Datasheet PDF文件第2页浏览型号MC74HCT373ANG的Datasheet PDF文件第3页浏览型号MC74HCT373ANG的Datasheet PDF文件第4页浏览型号MC74HCT373ANG的Datasheet PDF文件第5页浏览型号MC74HCT373ANG的Datasheet PDF文件第6页浏览型号MC74HCT373ANG的Datasheet PDF文件第7页 
MC74HCT373A  
Octal 3-State Noninverting  
Transparent Latch with  
LSTTL-Compatible Inputs  
HighPerformance SiliconGate CMOS  
http://onsemi.com  
MARKING  
The MC74HCT373A may be used as a level converter for  
interfacing TTL or NMOS outputs to HighSpeed CMOS inputs.  
The HCT373A is identical in pinout to the LS373.  
DIAGRAMS  
The eight latches of the HCT373A are transparent Dtype latches.  
While the Latch Enable is high the Q outputs follow the Data Inputs.  
When Latch Enable is taken low, data meeting the setup and hold  
times becomes latched.  
The Output Enable does not affect the state of the latch, but when  
Output Enable is high, all outputs are forced to the highimpedance  
state. Thus, data may be latched even when the outputs are not  
enabled.  
The HCT373A is identical in function to the HCT573A, which has  
the input pins on the opposite side of the package from the output pins.  
This device is similar in function to the HCT533A, which has  
inverting outputs.  
20  
20  
PDIP20  
N SUFFIX  
CASE 738  
MC74HCT373AN  
AWLYYWWG  
1
1
20  
SOIC20  
DW SUFFIX  
CASE 751D  
HCT373A  
AWLYYWWG  
20  
1
1
20  
Output Drive Capability: 15 LSTTL Loads  
HCT  
373A  
ALYWG  
G
TSSOP20  
DT SUFFIX  
CASE 948E  
20  
TTL/NMOSCompatible Input Levels  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
Low Input Current: 1.0 mA  
1
1
20  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7 A  
Chip Complexity: 196 FETs or 49 Equivalent Gates  
These Devices are PbFree and are RoHS Compliant  
SOEIAJ20  
F SUFFIX  
CASE 967  
20  
74HCT373A  
AWLYWWG  
1
1
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
WW, W = Work Week  
G or G  
= PbFree Package  
(Note: Microdot may be in either location)  
ORDERING INFORMATION  
Device  
Package  
PDIP20  
SOIC20  
Shipping  
18 / Box  
38 / Rail  
MC74HCT373ANG  
MC74HCT373ADWG  
MC74HCT373ADWR2G  
MC74HCT373AFELG  
SOIC20 1000 / Reel  
SOEIAJ20 2000 / Reel  
MC74HCT373ADTR2G TSSOP20 2500 / Reel  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
© Semiconductor Components Industries, LLC, 2011  
1
Publication Order Number:  
June, 2011 Rev. 12  
MC74HCT373A/D  

MC74HCT373ANG 替代型号

型号 品牌 替代类型 描述 数据表
CD74HCT373E TI

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High Speed CMOS Logic Octal Transparent Latch, Three-State Output
SN74HCT373N TI

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OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74HCT373DW TI

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OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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