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MC74HCT373AND PDF预览

MC74HCT373AND

更新时间: 2024-11-21 13:11:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 锁存器
页数 文件大小 规格书
8页 196K
描述
HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP20, PLASTIC, DIP-20

MC74HCT373AND 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:PLASTIC, DIP-20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.3
系列:HCTJESD-30 代码:R-PDIP-T20
JESD-609代码:e0长度:26.415 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):48 ns
认证状态:Not Qualified座面最大高度:4.57 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm

MC74HCT373AND 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 732–03  
20  
20  
High–Performance Silicon–Gate CMOS  
The MC54/74HCT373A may be used as a level converter for  
interfacing TTL or NMOS outputs to High–Speed CMOS inputs.  
The HCT373A is identical in pinout to the LS373.  
The eight latches of the HCT373A are transparent D–type latches.  
While the Latch Enable is high the Q outputs follow the Data Inputs. When  
Latch Enable is taken low, data meeting the setup and hold times  
becomes latched.  
The Output Enable does not affect the state of the latch, but when  
Output Enable is high, all outputs are forced to the high–impedance state.  
Thus, data may be latched even when the outputs are not enabled.  
The HCT373A is identical in function to the HCT573A, which has the  
input pins on the opposite side of the package from the output pins. This  
device is similar in function to the HCT533A, which has inverting outputs.  
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
1
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
20  
20  
1
SD SUFFIX  
SSOP PACKAGE  
CASE 940C–03  
1
DT SUFFIX  
TSSOP PACKAGE  
CASE 948E–02  
1
Output Drive Capability: 15 LSTTL Loads  
TTL/NMOS–Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
Low Input Current: 1.0 µA  
ORDERING INFORMATION  
MC54HCTXXXAJ  
MC74HCTXXXAN  
MC74HCTXXXADW  
MC74HCTXXXASD  
MC74HCTXXXADT  
Ceramic  
Plastic  
SOIC  
SSOP  
TSSOP  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
Chip Complexity: 196 FETs or 49 Equivalent Gates  
LOGIC DIAGRAM  
PIN ASSIGNMENT  
OUTPUT  
ENABLE  
Q0  
1
20  
V
CC  
3
2
5
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
D0  
D1  
D2  
D3  
D4  
2
3
19  
18  
Q7  
D7  
4
D0  
D1  
6
7
4
17  
D6  
8
9
Q1  
Q2  
5
16  
15  
14  
13  
12  
11  
Q6  
Q5  
D5  
D4  
Q4  
DATA  
INPUTS  
NONINVERTING  
OUTPUTS  
6
13  
12  
15  
16  
19  
D2  
7
14  
17  
18  
D5  
D6  
D7  
D3  
8
Q3  
9
LATCH  
ENABLE  
GND  
10  
11  
1
PIN 20 = V  
CC  
PIN 10 = GND  
LATCH ENABLE  
OUTPUT ENABLE  
FUNCTION TABLE  
Inputs  
Output  
Design Criteria  
Internal Gate Count*  
Value  
49  
Units  
ea.  
ns  
Output Latch  
Enable Enable  
D
Q
L
L
L
H
H
L
H
L
X
X
H
Internal Gate Propagation Delay  
Internal Gate Power Dissipation  
1.5  
L
No Change  
Z
5.0  
µW  
pJ  
H
X
X = don’t care  
Z = high impedance  
Speed Power Product  
.0075  
* Equivalent to a two–input NAND gate.  
2/97  
REV 7  
Motorola, Inc. 1997  

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