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MC74HCT373AN PDF预览

MC74HCT373AN

更新时间: 2024-11-20 23:01:35
品牌 Logo 应用领域
安森美 - ONSEMI 锁存器逻辑集成电路光电二极管驱动
页数 文件大小 规格书
8页 188K
描述
Octal 3-State Noninverting Transceiver Latch with LSTTL-Compatible Inputs

MC74HCT373AN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP20,.3
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:7.18系列:HCT
JESD-30 代码:R-PDIP-T20JESD-609代码:e0
长度:26.415 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.006 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:42 ns
传播延迟(tpd):48 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

MC74HCT373AN 数据手册

 浏览型号MC74HCT373AN的Datasheet PDF文件第2页浏览型号MC74HCT373AN的Datasheet PDF文件第3页浏览型号MC74HCT373AN的Datasheet PDF文件第4页浏览型号MC74HCT373AN的Datasheet PDF文件第5页浏览型号MC74HCT373AN的Datasheet PDF文件第6页浏览型号MC74HCT373AN的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
http://onsemi.com  
The MC74HCT373A may be used as a level converter for  
interfacing TTL or NMOS outputs to High–Speed CMOS inputs.  
The HCT373A is identical in pinout to the LS373.  
MARKING  
DIAGRAMS  
20  
The eight latches of the HCT373A are transparent D–type latches.  
While the Latch Enable is high the Q outputs follow the Data Inputs.  
When Latch Enable is taken low, data meeting the setup and hold  
times becomes latched.  
PDIP–20  
N SUFFIX  
CASE 738  
MC74HCT373AN  
AWLYYWW  
20  
1
The Output Enable does not affect the state of the latch, but when  
Output Enable is high, all outputs are forced to the high–impedance  
state. Thus, data may be latched even when the outputs are not  
enabled.  
The HCT373A is identical in function to the HCT573A, which has  
the input pins on the opposite side of the package from the output pins.  
This device is similar in function to the HCT533A, which has  
inverting outputs.  
1
20  
SOIC WIDE–20  
DW SUFFIX  
CASE 751D  
HCT373A  
AWLYYWW  
20  
1
1
20  
HCT  
373A  
ALYW  
TSSOP–20  
DT SUFFIX  
CASE 948G  
20  
1
Output Drive Capability: 15 LSTTL Loads  
TTL/NMOS–Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
Low Input Current: 1.0 µA  
1
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
PIN ASSIGNMENT  
Chip Complexity: 196 FETs or 49 Equivalent Gates  
ENABLE A  
A1  
1
2
3
4
5
6
7
8
9
20  
V
CC  
19 ENABLE B  
18 YA1  
17 B4  
YB4  
A2  
YB3  
A3  
16 YA2  
15 B3  
YB2  
A4  
14 YA3  
13 B2  
YB1  
12 YA4  
11 B1  
GND 10  
ORDERING INFORMATION  
Device  
Package  
PDIP–20  
Shipping  
MC74HCT373AN  
1440 / Box  
38 / Rail  
MC74HCT373ADW  
SOIC–WIDE  
MC74HCT373ADWR2 SOIC–WIDE 1000 / Reel  
MC74HCT373ADT  
TSSOP–20  
75 / Rail  
MC74HCT373ADTR2  
TSSOP–20 2500 / Reel  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 8  
MC74HCT373A/D  

MC74HCT373AN 替代型号

型号 品牌 替代类型 描述 数据表
SN74HCT373N TI

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SN74HCT373DW TI

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OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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