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MC74HCT245AN

更新时间: 2024-11-23 23:01:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 194K
描述
Octal 3-State Noninverting Bus Transceiver with LSTTL Compatible Inputs

MC74HCT245AN 技术参数

生命周期:Transferred零件包装代码:DIP
包装说明:DIP,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.06Is Samacsys:N
系列:HCTJESD-30 代码:R-PDIP-T20
JESD-609代码:e0长度:26.415 mm
逻辑集成电路类型:BUS TRANSCEIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE传播延迟(tpd):33 ns
认证状态:Not Qualified座面最大高度:4.57 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

MC74HCT245AN 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 732–03  
20  
20  
High–Performance Silicon–Gate CMOS  
1
The MC54/74HCT245A is identical in pinout to the LS245. This device  
may be used as a level converter for interfacing TTL or NMOS outputs to  
High Speed CMOS inputs.  
The MC54/74HCT245A is a 3–state noninverting transceiver that is  
used for 2–way asynchronous communication between data buses. The  
device has an active–low Output Enable pin, which is used to place the  
I/O ports into high–impedance states. The Direction control determines  
whether data flows from A to B or from B to A.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
1
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
20  
20  
1
SD SUFFIX  
SSOP PACKAGE  
CASE 940C–03  
Output Drive Capability: 15 LSTTL Loads  
TTL/NMOS Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
Low Input Current: 1.0 µA  
1
DT SUFFIX  
TSSOP PACKAGE  
CASE 948E–02  
1
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
ORDERING INFORMATION  
MC54HCTXXXAJ  
MC74HCTXXXAN  
MC74HCTXXXADW  
MC74HCTXXXASD  
MC74HCTXXXADT  
Ceramic  
Plastic  
SOIC  
SSOP  
TSSOP  
Chip Complexity: 304 FETs or 76 Equivalent Gates  
LOGIC DIAGRAM  
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
PIN ASSIGNMENT  
A
B
DATA  
PORT  
DATA  
PORT  
DIRECTION  
1
20  
V
CC  
A1  
A2  
A3  
2
3
4
19  
18  
17  
OUTPUT ENABLE  
B1  
B2  
A4  
A5  
A6  
5
6
7
16  
15  
14  
B3  
B4  
B5  
1
DIRECTION  
PIN 20 = V  
CC  
PIN 10 = GND  
19  
OUTPUT ENABLE  
A7  
A8  
8
13  
12  
11  
B6  
B7  
B8  
9
Design Criteria  
Internal Gate Count*  
Value Units  
GND  
10  
76  
1.0  
ea  
ns  
Internal Gate Propagation Delay  
Internal Gate Power Dissipation  
Speed Power Product  
FUNCTION TABLE  
5.0  
µW  
Control Inputs  
Output  
0.005  
pJ  
Enable  
Direction  
Operation  
* Equivalent to a two–input NAND gate.  
L
L
L
H
X
Data Transmitted from Bus B to Bus A  
Data Transmitted from Bus A to Bus B  
Buses Isolated (High–Impedance State)  
H
X = Don’t Care  
2/97  
REV 7  
Motorola, Inc. 1997  

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