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MC74HCT245ADT PDF预览

MC74HCT245ADT

更新时间: 2024-09-14 23:01:35
品牌 Logo 应用领域
安森美 - ONSEMI 总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 184K
描述
Octal 3-State Noninverting Bus Transceiver with LSTTL Compatible Inputs

MC74HCT245ADT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP20,.25
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.07
控制类型:COMMON CONTROL计数方向:BIDIRECTIONAL
系列:HCTJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:6.5 mm
逻辑集成电路类型:BUS TRANSCEIVER最大I(ol):0.006 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:RAIL峰值回流温度(摄氏度):260
电源:5 VProp。Delay @ Nom-Sup:33 ns
传播延迟(tpd):33 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40翻译:N/A
宽度:4.4 mmBase Number Matches:1

MC74HCT245ADT 数据手册

 浏览型号MC74HCT245ADT的Datasheet PDF文件第2页浏览型号MC74HCT245ADT的Datasheet PDF文件第3页浏览型号MC74HCT245ADT的Datasheet PDF文件第4页浏览型号MC74HCT245ADT的Datasheet PDF文件第5页浏览型号MC74HCT245ADT的Datasheet PDF文件第6页浏览型号MC74HCT245ADT的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74HCT245A is identical in pinout to the LS245. This  
device may be used as a level converter for interfacing TTL or NMOS  
outputs to High Speed CMOS inputs.  
http://onsemi.com  
The MC74HCT245A is a 3–state noninverting transceiver that is  
used for 2–way asynchronous communication between data buses.  
The device has an active–low Output Enable pin, which is used to  
place the I/O ports into high–impedance states. The Direction control  
determines whether data flows from A to B or from B to A.  
Output Drive Capability: 15 LSTTL Loads  
TTL/NMOS Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
Low Input Current: 1.0 µA  
MARKING  
DIAGRAMS  
20  
PDIP–20  
N SUFFIX  
CASE 738  
MC74HCT245AN  
AWLYYWW  
20  
1
1
20  
SOIC WIDE–20  
DW SUFFIX  
CASE 751D  
HCT245A  
AWLYYWW  
20  
1
1
20  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
HCT  
245A  
ALYW  
TSSOP–20  
DT SUFFIX  
CASE 948G  
20  
Chip Complexity: 304 FETs or 76 Equivalent Gates  
1
LOGIC DIAGRAM  
1
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
A
DATA  
PORT  
B
DATA  
PORT  
PIN ASSIGNMENT  
DIRECTION  
1
2
3
4
5
6
7
8
9
20  
V
CC  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
19 OUTPUT ENABLE  
18 B1  
1
DIRECTION  
PIN 20 = V  
CC  
PIN 10 = GND  
17 B2  
19  
OUTPUT ENABLE  
16 B3  
Design Criteria  
Internal Gate Count*  
Value Units  
15 B4  
76  
1.0  
ea  
ns  
14 B5  
Internal Gate Propagation Delay  
Internal Gate Power Dissipation  
Speed Power Product  
13 B6  
12 B7  
5.0  
µW  
pJ  
GND 10  
11 B8  
0.005  
*Equivalent to a two–input NAND gate.  
FUNCTION TABLE  
ORDERING INFORMATION  
Control Inputs  
Output  
Device  
Package  
PDIP–20  
Shipping  
Enable  
Direction  
Operation  
MC74HCT245AN  
1440 / Box  
38 / Rail  
L
L
L
H
X
Data Transmitted from Bus B to Bus A  
Data Transmitted from Bus A to Bus B  
Buses Isolated (High–Impedance State)  
MC74HCT245ADW  
SOIC–WIDE  
MC74HCT245ADWR2 SOIC–WIDE 1000 / Reel  
MC74HCT245ADT  
TSSOP–20  
75 / Rail  
H
X = Don’t Care  
MC74HCT245ADTR2  
TSSOP–20 2500 / Reel  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 8  
MC74HCT245A/D  

MC74HCT245ADT 替代型号

型号 品牌 替代类型 描述 数据表
MC74HCT245ADTR2 ONSEMI

完全替代

Octal 3-State Noninverting Bus Transceiver with LSTTL Compatible Inputs
MM74HCT245MTCX ONSEMI

类似代替

八路 3 态收发器
MM74HCT245MTC ONSEMI

类似代替

八路 3 态收发器

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