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MC74HCT245

更新时间: 2024-09-13 23:01:35
品牌 Logo 应用领域
安森美 - ONSEMI 总线收发器
页数 文件大小 规格书
8页 184K
描述
Octal 3-State Noninverting Bus Transceiver with LSTTL Compatible Inputs

MC74HCT245 数据手册

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High–Performance Silicon–Gate CMOS  
The MC74HCT245A is identical in pinout to the LS245. This  
device may be used as a level converter for interfacing TTL or NMOS  
outputs to High Speed CMOS inputs.  
http://onsemi.com  
The MC74HCT245A is a 3–state noninverting transceiver that is  
used for 2–way asynchronous communication between data buses.  
The device has an active–low Output Enable pin, which is used to  
place the I/O ports into high–impedance states. The Direction control  
determines whether data flows from A to B or from B to A.  
Output Drive Capability: 15 LSTTL Loads  
TTL/NMOS Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
Low Input Current: 1.0 µA  
MARKING  
DIAGRAMS  
20  
PDIP–20  
N SUFFIX  
CASE 738  
MC74HCT245AN  
AWLYYWW  
20  
1
1
20  
SOIC WIDE–20  
DW SUFFIX  
CASE 751D  
HCT245A  
AWLYYWW  
20  
1
1
20  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
HCT  
245A  
ALYW  
TSSOP–20  
DT SUFFIX  
CASE 948G  
20  
Chip Complexity: 304 FETs or 76 Equivalent Gates  
1
LOGIC DIAGRAM  
1
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
A
DATA  
PORT  
B
DATA  
PORT  
PIN ASSIGNMENT  
DIRECTION  
1
2
3
4
5
6
7
8
9
20  
V
CC  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
19 OUTPUT ENABLE  
18 B1  
1
DIRECTION  
PIN 20 = V  
CC  
PIN 10 = GND  
17 B2  
19  
OUTPUT ENABLE  
16 B3  
Design Criteria  
Internal Gate Count*  
Value Units  
15 B4  
76  
1.0  
ea  
ns  
14 B5  
Internal Gate Propagation Delay  
Internal Gate Power Dissipation  
Speed Power Product  
13 B6  
12 B7  
5.0  
µW  
pJ  
GND 10  
11 B8  
0.005  
*Equivalent to a two–input NAND gate.  
FUNCTION TABLE  
ORDERING INFORMATION  
Control Inputs  
Output  
Device  
Package  
PDIP–20  
Shipping  
Enable  
Direction  
Operation  
MC74HCT245AN  
1440 / Box  
38 / Rail  
L
L
L
H
X
Data Transmitted from Bus B to Bus A  
Data Transmitted from Bus A to Bus B  
Buses Isolated (High–Impedance State)  
MC74HCT245ADW  
SOIC–WIDE  
MC74HCT245ADWR2 SOIC–WIDE 1000 / Reel  
MC74HCT245ADT  
TSSOP–20  
75 / Rail  
H
X = Don’t Care  
MC74HCT245ADTR2  
TSSOP–20 2500 / Reel  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 8  
MC74HCT245A/D  

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