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MC74HCT241AN PDF预览

MC74HCT241AN

更新时间: 2024-09-09 23:01:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 驱动器
页数 文件大小 规格书
7页 152K
描述
Octal 3-State Noninverting Buffer/Line Driver/Line Receiver with LSTTL-Compatible Inputs

MC74HCT241AN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP,
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.23
其他特性:OUTPUT ENABLE ACTIVE HIGH FOR ONE FUNCTION系列:HCT
JESD-30 代码:R-PDIP-T20JESD-609代码:e0
长度:26.415 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):35 ns认证状态:Not Qualified
座面最大高度:4.57 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

MC74HCT241AN 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 732–03  
20  
20  
1
High–Performance Silicon–Gate CMOS  
The MC54/74HCT241A is identical in pinout to the LS241. This device  
may be used as a level converter for interfacing TTL or NMOS outputs to  
High–Speed CMOS inputs. The HCT241A is an octal noninverting buffer/line  
driver/line receiver designed to be used with 3–state memory address  
drivers, clock drivers, and other bus–oriented systems. The device has  
non–inverted outputs and two output enables. Enable A is active–low and  
Enable B is active–high.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
1
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
1
The HCT241A is similar in function to the HCT244. See also HCT240.  
Output Drive Capability: 15 LSTTL Loads  
TTL/NMOS–Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
Low Input Current: 1 µA  
ORDERING INFORMATION  
MC54HCTXXXAJ  
MC74HCTXXXAN  
Ceramic  
Plastic  
MC74HCTXXXADW SOIC  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
PIN ASSIGNMENT  
Chip Complexity: 118 FETs or 29.5 Equivalent Gates  
ENABLE A  
1
20  
V
CC  
LOGIC DIAGRAM  
A1  
YB4  
A2  
2
3
4
19  
18  
17  
ENABLE B  
YA1  
2
4
6
8
18  
16  
14  
12  
A1  
A2  
A3  
A4  
YA1  
YA2  
YA3  
YA4  
B4  
YB3  
A3  
5
16  
15  
14  
13  
12  
11  
YA2  
B3  
6
YB2  
A4  
7
YA3  
B2  
8
NONINVERTING  
OUTPUTS  
YB1  
GND  
9
YA4  
B1  
DATA INPUTS  
11  
13  
15  
17  
9
7
5
3
10  
B1  
B2  
YB1  
YB2  
FUNCTION TABLE  
B3  
B4  
YB3  
YB4  
Inputs  
Enable A  
Output  
A
YA  
L
L
H
L
H
X
L
H
Z
PIN 20 = V  
CC  
PIN 10 = GND  
1
Inputs  
Output  
YB  
ENABLE A  
ENABLE B  
OUTPUT  
ENABLES  
19  
Enable B  
B
H
H
L
L
H
X
L
H
Z
Z = high impedance  
X = don’t care  
2/97  
Motorola, Inc. 1997  
REV 7  

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