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MC74HCT132ANG PDF预览

MC74HCT132ANG

更新时间: 2024-10-31 11:07:51
品牌 Logo 应用领域
安森美 - ONSEMI 触发器
页数 文件大小 规格书
9页 165K
描述
Quad 2-Input NAND Gate with Schmitt-Trigger Inputs with LSTTL Compatible Inputs

MC74HCT132ANG 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.73
系列:HCTJESD-30 代码:R-PDIP-T14
长度:18.86 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE最大I(ol):0.004 A
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:AMMO PACK
电源:5 VProp。Delay @ Nom-Sup:38 ns
传播延迟(tpd):38 ns认证状态:Not Qualified
施密特触发器:YES座面最大高度:4.69 mm
子类别:Gates最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

MC74HCT132ANG 数据手册

 浏览型号MC74HCT132ANG的Datasheet PDF文件第2页浏览型号MC74HCT132ANG的Datasheet PDF文件第3页浏览型号MC74HCT132ANG的Datasheet PDF文件第4页浏览型号MC74HCT132ANG的Datasheet PDF文件第5页浏览型号MC74HCT132ANG的Datasheet PDF文件第6页浏览型号MC74HCT132ANG的Datasheet PDF文件第7页 
MC74HCT132A  
Quad 2-Input NAND Gate  
with Schmitt-Trigger Inputs  
with LSTTL Compatible  
Inputs  
http://onsemi.com  
HighPerformance SiliconGate CMOS  
MARKING  
DIAGRAMS  
The MC74HCT132A is identical in pinout to the LS132. The device  
inputs are compatible with standard CMOS outputs; with pullup  
resistors, they are compatible with LSTTL outputs.  
The MC74HCT132A can be used to enhance noise immunity or to  
square up slowly changing waveforms.  
14  
PDIP14  
N SUFFIX  
CASE 646  
MC74HCT132AN  
AWLYYWWG  
1
Features  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
14  
SOIC14  
D SUFFIX  
CASE 751A  
HCT132AG  
AWLYWW  
Low Input Current: 1.0 mA  
1
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements as Defined by JEDEC  
14  
Standard No. 7A  
HCT  
132A  
ALYWG  
G
TSSOP14  
DT SUFFIX  
CASE 948G  
Chip Complexity: 72 FETs or 18 Equivalent Gates  
These are PbFree Devices  
1
A1  
B1  
1
2
14  
13 B4  
12  
V
CC  
14  
74HCT132A  
ALYWG  
SOEIAJ14  
F SUFFIX  
CASE 965  
Y1  
A2  
3
4
A4  
11 Y4  
10 B3  
1
B2  
Y2  
5
6
9
8
A3  
Y3  
A
= Assembly Location  
L, WL = Wafer Lot  
Y, YY = Year  
GND  
7
W, WW = Work Week  
Figure 1. Pin Assignment  
G or G = PbFree Package  
(Note: Microdot may be in either location)  
FUNCTION TABLE  
Inputs  
Output  
Y
A
B
L
L
H
H
L
H
L
H
H
H
L
H
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
© Semiconductor Components Industries, LLC, 2009  
1
Publication Order Number:  
November, 2009 Rev. 1  
MC74HCT132A/D  

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