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MC74HCT132A

更新时间： 2024-09-13 11:07:51

品牌	Logo	应用领域
安森美 - ONSEMI		触发器栅
页数	文件大小	规格书
9页	165K
描述
Quad 2-Input NAND Gate with Schmitt-Trigger Inputs with LSTTL Compatible Inputs

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MC74HCT132A 数据手册

MC74HCT132A

Quad 2-Input NAND Gate

with Schmitt-Trigger Inputs

with LSTTL Compatible

Inputs

http://onsemi.com

High−Performance Silicon−Gate CMOS

MARKING

DIAGRAMS

The MC74HCT132A is identical in pinout to the LS132. The device

inputs are compatible with standard CMOS outputs; with pull−up

resistors, they are compatible with LSTTL outputs.

The MC74HCT132A can be used to enhance noise immunity or to

square up slowly changing waveforms.

PDIP−14

N SUFFIX

CASE 646

MC74HCT132AN

AWLYYWWG

Features

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

SOIC−14

D SUFFIX

CASE 751A

HCT132AG

AWLYWW

• Low Input Current: 1.0 mA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements as Defined by JEDEC

Standard No. 7A

HCT

132A

ALYWG

TSSOP−14

DT SUFFIX

CASE 948G

• Chip Complexity: 72 FETs or 18 Equivalent Gates

• These are Pb−Free Devices

13 B4

74HCT132A

ALYWG

SOEIAJ−14

F SUFFIX

CASE 965

11 Y4

10 B3

= Assembly Location

L, WL = Wafer Lot

Y, YY = Year

GND

W, WW = Work Week

Figure 1. Pin Assignment

G or G = Pb−Free Package

(Note: Microdot may be in either location)

FUNCTION TABLE

Inputs

Output

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

Publication Order Number:

November, 2009 − Rev. 1

MC74HCT132A/D

12 3 4 5 6 7...9

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