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MC74HCT08ADTG PDF预览

MC74HCT08ADTG

更新时间: 2024-10-31 13:11:19
品牌 Logo 应用领域
安森美 - ONSEMI
页数 文件大小 规格书
7页 142K
描述
Quad 2-Input AND Gate with LSTTL Compatible Inputs, TSSOP-14, 96-TUBE

MC74HCT08ADTG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active包装说明:TSSOP, TSSOP14,.25
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.67Is Samacsys:N
系列:HCTJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:AND GATE
最大I(ol):0.004 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:26 ns
传播延迟(tpd):26 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.2 mm
子类别:Gates最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

MC74HCT08ADTG 数据手册

 浏览型号MC74HCT08ADTG的Datasheet PDF文件第2页浏览型号MC74HCT08ADTG的Datasheet PDF文件第3页浏览型号MC74HCT08ADTG的Datasheet PDF文件第4页浏览型号MC74HCT08ADTG的Datasheet PDF文件第5页浏览型号MC74HCT08ADTG的Datasheet PDF文件第6页浏览型号MC74HCT08ADTG的Datasheet PDF文件第7页 
MC74HCT08A  
Quad 2-Input AND Gate  
with LSTTL Compatible  
Inputs  
HighPerformance SiliconGate CMOS  
http://onsemi.com  
MARKING  
The MC74HCT08A is identical in pinout to the LS08. The device  
inputs are compatible with Standard CMOS or LSTTL outputs.  
DIAGRAMS  
Features  
14  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 2.0 V to 6.0 V  
Low Input Current: 1 mA  
PDIP14  
N SUFFIX  
CASE 646  
MC74HCT08AN  
AWLYYWWG  
14  
1
1
High Noise Immunity Characteristic of CMOS Devices  
In Compliance With the JEDEC Standard No. 7A Requirements  
Chip Complexity: 24 FETs or 6 Equivalent Gates  
These are PbFree Devices  
14  
SOIC14  
D SUFFIX  
HCT08AG  
AWLYWW  
14  
CASE 751A  
1
1
1
A1  
3
14  
Y1  
Y2  
Y3  
Y4  
2
B1  
HCT  
08  
TSSOP14  
DT SUFFIX  
CASE 948G  
14  
4
5
A2  
B2  
ALYW G  
6
8
1
G
1
Y = AB  
9
A3  
B3  
A
= Assembly Location  
10  
WL, L = Wafer Lot  
YY, Y = Year  
WW, W = Work Week  
12  
13  
A4  
B4  
G or G = PbFree Package  
11  
(Note: Microdot may be in either location)  
PIN 14 = V  
PIN 7 = GND  
CC  
FUNCTION TABLE  
Inputs  
Output  
Y
Figure 1. Logic Diagram  
A
B
L
L
H
H
L
H
L
L
L
L
Pinout: 14Lead Packages (Top View)  
V
CC  
B4  
13  
A4  
12  
Y4  
11  
B3  
10  
A3  
9
Y3  
8
H
H
14  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
1
2
3
4
5
6
7
A1  
B1  
Y1  
A2  
B2  
Y2 GND  
Figure 2. Pinout  
© Semiconductor Components Industries, LLC, 2009  
1
Publication Order Number:  
November, 2009 Rev. 8  
MC74HCT08A/D  

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