Datasheet > MC74HC74A_06

MC74HC74A_06

更新时间： 2024-09-23 05:09:55

品牌	Logo	应用领域
安森美 - ONSEMI		触发器栅
页数	文件大小	规格书
9页	179K
描述
Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS

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MC74HC74A_06 数据手册

MC74HC74A

Dual D Flip−Flop with Set

and Reset

High−Performance Silicon−Gate CMOS

The MC74HC74A is identical in pinout to the LS74. The device

inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LSTTL outputs.

This device consists of two D flip−flops with individual Set, Reset,

and Clock inputs. Information at a D−input is transferred to the

corresponding Q output on the next positive going edge of the clock

input. Both Q and Q outputs are available from each flip−flop. The Set

and Reset inputs are asynchronous.

http://onsemi.com

MARKING

DIAGRAMS

PDIP−14

N SUFFIX

CASE 646

MC74HC74AN

AWLYYWWG

Features

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

SOIC−14

D SUFFIX

CASE 751A

HC74AG

AWLYWW

• Low Input Current: 1.0 mA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the JEDEC Standard No. 7.0 A Requirements

• Chip Complexity: 128 FETs or 32 Equivalent Gates

• Pb−Free Packages are Available

74A

ALYWG

TSSOP−14

DT SUFFIX

CASE 948G

SOEIAJ−14

F SUFFIX

CASE 965

74HC74A

ALYWG

L, WL

Y, YY

= Assembly Location

= Wafer Lot

= Year

W, WW = Work Week

G or G

= Pb−Free Package

(Note: Microdot may be in either location)

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

Publication Order Number:

October, 2006 − Rev. 11

MC74HC74A/D

12 3 4 5 6 7...9

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