High–Performance Silicon–Gate CMOS
The MC74HC74A is identical in pinout to the LS74. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two D flip–flops with individual Set, Reset,
and Clock inputs. Information at a D–input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip–flop. The Set
and Reset inputs are asynchronous.
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MARKING
DIAGRAMS
14
PDIP–14
N SUFFIX
CASE 646
MC74HC74AN
AWLYYWW
1
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
14
SOIC–14
D SUFFIX
CASE 751A
HC74A
AWLYWW
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
1
14
HC
74A
ALYW
TSSOP–14
DT SUFFIX
CASE 948G
• Chip Complexity: 128 FETs or 32 Equivalent Gates
LOGIC DIAGRAM
1
1
RESET 1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
5
6
2
3
DATA 1
Q1
Q1
CLOCK 1
PIN ASSIGNMENT
4
SET 1
PIN 14 = V
CC
PIN 7 = GND
RESET 1
DATA 1
1
2
14
13 RESET 2
12
V
CC
13
RESET 2
3
4
CLOCK 1
SET 1
DATA 2
9
8
12
11
DATA 2
Q2
Q2
11 CLOCK 2
10 SET 2
CLOCK 2
Q1
Q1
5
6
10
9
8
Q2
Q2
SET 2
GND
7
FUNCTION TABLE
Inputs
Set Reset Clock Data
Outputs
Q
Q
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
H
L
X
X
X
H
L
H*
H
L
L
H
H*
L
ORDERING INFORMATION
Device
Package
PDIP–14
Shipping
MC74HC74AN
2000 / Box
55 / Rail
H
L
H
No Change
No Change
No Change
MC74HC74AD
SOIC–14
SOIC–14
TSSOP–14
TSSOP–14
MC74HC74ADR2
MC74HC74ADT
MC74HC74ADTR2
2500 / Reel
96 / Rail
*Both outputs will remain high as long as Set and Reset are low, but the output
states are unpredictable if Set and Reset go high simultaneously.
2500 / Reel
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 8
MC74HC74A/D