5秒后页面跳转
MC74HC73N PDF预览

MC74HC73N

更新时间: 2024-09-22 23:01:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 174K
描述
Dual J-K Flip-Flop with Reset

MC74HC73N 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP,
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.66
Is Samacsys:N其他特性:MASTER SLAVE OPERATION
系列:HC/UHJESD-30 代码:R-PDIP-T14
JESD-609代码:e0长度:18.86 mm
负载电容(CL):50 pF逻辑集成电路类型:J-K FLIP-FLOP
位数:2功能数量:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):38 ns
认证状态:Not Qualified座面最大高度:4.69 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:NEGATIVE EDGE
宽度:7.62 mm最小 fmax:20 MHz
Base Number Matches:1

MC74HC73N 数据手册

 浏览型号MC74HC73N的Datasheet PDF文件第2页浏览型号MC74HC73N的Datasheet PDF文件第3页浏览型号MC74HC73N的Datasheet PDF文件第4页浏览型号MC74HC73N的Datasheet PDF文件第5页 
SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
The MC74HC73 is identical in pinout to the LS73. The device inputs are  
compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 646–06  
14  
Each flip flop is negative–edge clocked and has an active–low asynchro-  
nous reset.  
1
The MC74HC73 is identical in function to the HC107, but has a different  
pinout.  
D SUFFIX  
SOIC PACKAGE  
CASE 751A–03  
14  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
1
ORDERING INFORMATION  
Low Input Current: 1 µA  
MC74HCXXN  
MC74HCXXD  
Plastic  
SOIC  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
Chip Complexity: 92 FETs or 23 Equivalent Gates  
PIN ASSIGNMENT  
J1  
CLOCK 1  
RESET 1  
K1  
1
2
14  
13  
LOGIC DIAGRAM  
Q1  
3
4
12  
11  
Q1  
14  
V
GND  
CC  
J1  
CLOCK 1  
K1  
12  
13  
Q1  
Q1  
CLOCK 2  
RESET 2  
5
6
10  
9
K2  
Q2  
1
3
2
J2  
7
8
Q2  
RESET 1  
7
5
J2  
CLOCK 2  
K2  
9
8
Q2  
Q2  
FUNCTION TABLE  
Inputs  
Reset Clock  
Outputs  
10  
6
J
K
Q
Q
L
X
X
L
X
L
L
H
RESET 2  
H
H
H
H
H
H
H
No Change  
PIN 4 = V  
CC  
PIN 11 = GND  
L
H
L
H
X
X
X
L
H
H
L
H
H
X
X
X
Toggle  
L
H
No Change  
No Change  
No Change  
10/95  
REV 6  
Motorola, Inc. 1995  

与MC74HC73N相关器件

型号 品牌 获取价格 描述 数据表
MC74HC73ND MOTOROLA

获取价格

HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14
MC74HC73NDS MOTOROLA

获取价格

暂无描述
MC74HC73NS MOTOROLA

获取价格

暂无描述
MC74HC73NS ROCHESTER

获取价格

J-K Flip-Flop
MC74HC74 ONSEMI

获取价格

Dual D Flip-Flop with Set and Reset
MC74HC74A ONSEMI

获取价格

Dual D Flip-Flop with Set and Reset
MC74HC74A_06 ONSEMI

获取价格

Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS
MC74HC74A_11 ONSEMI

获取价格

Dual D Flip-Flop with Set and Reset
MC74HC74AD MOTOROLA

获取价格

Dual D Flip-Flop with Set and Reset
MC74HC74AD ONSEMI

获取价格

Dual D Flip-Flop with Set and Reset