MC74HC73D-TR

更新时间： 2024-09-23 13:11:23

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		触发器
页数	文件大小	规格书
5页	174K
描述
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数据手册

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MC74HC73D-TR 数据手册

SEMICONDUCTOR TECHNICAL DATA

High–Performance Silicon–Gate CMOS

The MC74HC73 is identical in pinout to the LS73. The device inputs are

compatible with standard CMOS outputs; with pullup resistors, they are

compatible with LSTTL outputs.

N SUFFIX

PLASTIC PACKAGE

CASE 646–06

Each flip flop is negative–edge clocked and has an active–low asynchro-

nous reset.

The MC74HC73 is identical in function to the HC107, but has a different

pinout.

D SUFFIX

SOIC PACKAGE

CASE 751A–03

•

Output Drive Capability: 10 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 2 to 6 V

ORDERING INFORMATION

Low Input Current: 1 µA

MC74HCXXN

MC74HCXXD

Plastic

SOIC

High Noise Immunity Characteristic of CMOS Devices

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

•

Chip Complexity: 92 FETs or 23 Equivalent Gates

PIN ASSIGNMENT

CLOCK 1

RESET 1

LOGIC DIAGRAM

GND

CLOCK 1

CLOCK 2

RESET 2

RESET 1

CLOCK 2

FUNCTION TABLE

Inputs

Reset Clock

Outputs

RESET 2

No Change

PIN 4 = V

PIN 11 = GND

Toggle

No Change

10/95

REV 6

Motorola, Inc. 1995

12 3 4 5

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与MC74HC73D-TR相关器件

型号	品牌	获取价格	描述	数据表
MC74HC73JD	ROCHESTER	获取价格	J-K Flip-Flop
MC74HC73JDS	ROCHESTER	获取价格	J-K Flip-Flop
MC74HC73N	MOTOROLA	获取价格	Dual J-K Flip-Flop with Reset
MC74HC73ND	MOTOROLA	获取价格	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14
MC74HC73NDS	MOTOROLA	获取价格	暂无描述
MC74HC73NS	MOTOROLA	获取价格	暂无描述
MC74HC73NS	ROCHESTER	获取价格	J-K Flip-Flop
MC74HC74	ONSEMI	获取价格	Dual D Flip-Flop with Set and Reset
MC74HC74A	ONSEMI	获取价格	Dual D Flip-Flop with Set and Reset
MC74HC74A_06	ONSEMI	获取价格	Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS