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MC74HC574A PDF预览

MC74HC574A

更新时间: 2024-02-18 10:46:52
品牌 Logo 应用领域
安森美 - ONSEMI 触发器
页数 文件大小 规格书
8页 181K
描述
Octal 3-State Noninverting D Flip-Flop

MC74HC574A 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP20,.3
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.15
其他特性:BROADSIDE VERSION OF 374系列:HC/UH
JESD-30 代码:R-PDIP-T20JESD-609代码:e0
长度:26.415 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:20000000 Hz
最大I(ol):0.006 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
传播延迟(tpd):53 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.62 mmBase Number Matches:1

MC74HC574A 数据手册

 浏览型号MC74HC574A的Datasheet PDF文件第2页浏览型号MC74HC574A的Datasheet PDF文件第3页浏览型号MC74HC574A的Datasheet PDF文件第4页浏览型号MC74HC574A的Datasheet PDF文件第5页浏览型号MC74HC574A的Datasheet PDF文件第6页浏览型号MC74HC574A的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74HC574A is identical in pinout to the LS574. The device  
inputs are compatible with standard CMOS outputs; with pullup  
resistors, they are compatible with LSTTL outputs.  
http://onsemi.com  
Data meeting the setup time is clocked to the outputs with the rising  
edge of the Clock. The Output Enable input does not affect the states  
of the flip–flops, but when Output Enable is high, all device outputs  
are forced to the high–impedance state. Thus, data may be stored even  
when the outputs are not enabled.  
The HC574A is identical in function to the HC374A but has the  
flip–flop inputs on the opposite side of the package from the outputs to  
facilitate PC board layout.  
MARKING  
DIAGRAMS  
20  
PDIP–20  
N SUFFIX  
CASE 738  
MC74HC574AN  
AWLYYWW  
20  
1
1
20  
SOIC WIDE–20  
DW SUFFIX  
CASE 751D  
HC574A  
AWLYYWW  
20  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 µA  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
1
1
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
Chip Complexity: 266 FETs or 66.5 Equivalent Gates  
ORDERING INFORMATION  
Device  
Package  
PDIP–20  
Shipping  
MC74HC574AN  
1440 / Box  
38 / Rail  
MC74HC574ADW  
MC74HC574ADWR2  
SOIC–WIDE  
SOIC–WIDE 1000 / Reel  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 8  
MC74HC574A/D  

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