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MC74HC573ADWR2 PDF预览

MC74HC573ADWR2

更新时间: 2024-11-20 23:01:35
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 203K
描述
Octal 3-State Noninverting Transparent Latch

MC74HC573ADWR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-20
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.16
Is Samacsys:N系列:HC/UH
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.006 A
湿度敏感等级:3位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):240
电源:2/6 VProp。Delay @ Nom-Sup:45 ns
传播延迟(tpd):240 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
Base Number Matches:1

MC74HC573ADWR2 数据手册

 浏览型号MC74HC573ADWR2的Datasheet PDF文件第2页浏览型号MC74HC573ADWR2的Datasheet PDF文件第3页浏览型号MC74HC573ADWR2的Datasheet PDF文件第4页浏览型号MC74HC573ADWR2的Datasheet PDF文件第5页浏览型号MC74HC573ADWR2的Datasheet PDF文件第6页浏览型号MC74HC573ADWR2的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74HC573A is identical in pinout to the LS573. The devices  
are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
http://onsemi.com  
These latches appear transparent to data (i.e., the outputs change  
asynchronously) when Latch Enable is high. When Latch Enable goes  
low, data meeting the setup and hold time becomes latched.  
The HC573A is identical in function to the HC373A but has the data  
inputs on the opposite side of the package from the outputs to facilitate  
PC board layout.  
MARKING  
DIAGRAMS  
20  
PDIP–20  
N SUFFIX  
CASE 738  
MC74HC573AN  
AWLYYWW  
20  
1
1
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 µA  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
20  
SOIC WIDE–20  
DW SUFFIX  
CASE 751D  
HC573A  
AWLYYWW  
20  
1
1
20  
HC  
573A  
ALYW  
TSSOP–20  
DT SUFFIX  
CASE 948E  
20  
Chip Complexity: 218 FETs or 54.5 Equivalent Gates  
1
1
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
ORDERING INFORMATION  
Device  
Package  
PDIP–20  
Shipping  
1440 / Box  
38 / Rail  
MC74HC573AN  
MC74HC573ADW  
MC74HC573ADWR2  
MC74HC573ADT  
MC74HC573ADTR2  
SOIC–WIDE  
SOIC–WIDE 1000 / Reel  
TSSOP–20 75 / Rail  
TSSOP–20 2500 / Reel  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
May, 2000 – Rev. 9  
MC74HC573A/D  

MC74HC573ADWR2 替代型号

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MM74HC573WM ONSEMI

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