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MC74HC564AN PDF预览

MC74HC564AN

更新时间: 2024-01-22 01:11:26
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器
页数 文件大小 规格书
8页 191K
描述
Octal 3-State Inverting D Flip-Flop

MC74HC564AN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP20,.3Reach Compliance Code:unknown
风险等级:5.92JESD-30 代码:R-PDIP-T20
JESD-609代码:e0逻辑集成电路类型:D FLIP-FLOP
功能数量:8端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:2/6 V认证状态:Not Qualified
子类别:FF/Latches表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
触发器类型:POSITIVE EDGEBase Number Matches:1

MC74HC564AN 数据手册

 浏览型号MC74HC564AN的Datasheet PDF文件第2页浏览型号MC74HC564AN的Datasheet PDF文件第3页浏览型号MC74HC564AN的Datasheet PDF文件第4页浏览型号MC74HC564AN的Datasheet PDF文件第5页浏览型号MC74HC564AN的Datasheet PDF文件第6页浏览型号MC74HC564AN的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
The MC74HC564A is identical in pinout to the LS564. The device inputs  
are compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
20  
1
This device is identical in function to the HC534A but has the flip–flop  
inputs on the opposite side of the package from the outputs to facilitate PC  
board layout.  
Data meeting the setup time is clocked, in inverted form, to the outputs  
with the rising edge of the Clock. The Output Enable input does not affect the  
states of the flip–flops, but when Output Enable is high, all device outputs are  
forced to the high–impedance state. Thus, data may be stored even when  
the outputs are not enabled.  
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
1
ORDERING INFORMATION  
MC74HCXXXAN Plastic  
MC74HCXXXADW SOIC  
The HC564A is the inverting version of the HC574A.  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
PIN ASSIGNMENT  
Low Input Current: 1 µA  
OUTPUT  
ENABLE  
1
20  
V
CC  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
D0  
D1  
D2  
2
3
4
19  
18  
17  
Q0  
Q1  
Q2  
Chip Complexity: 282 FETs or 70.5 Equivalent Gates  
D3  
D4  
5
16  
15  
14  
13  
12  
11  
Q3  
6
Q4  
LOGIC DIAGRAM  
D5  
7
Q5  
D6  
8
Q6  
2
3
4
5
6
7
8
19  
D0  
D1  
Q0  
D7  
9
Q7  
18  
17  
16  
15  
14  
13  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
GND  
10  
CLOCK  
D2  
D3  
D4  
D5  
D6  
DATA  
INPUTS  
INVERTING  
OUTPUTS  
FUNCTION TABLE  
Inputs  
Output  
9
11  
1
12  
Output  
Enable Clock  
D7  
Q7  
D
Q
CLOCK  
L
L
L
H
L
X
X
L
PIN 20 = V  
H
No Change  
Z
CC  
PIN 10 = GND  
OUTPUT  
ENABLE  
L,H,  
X
H
X = don’t care  
Z = high impedance  
9/96  
REV 0  
Motorola, Inc. 1996  

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