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MC74HC563ND PDF预览

MC74HC563ND

更新时间: 2024-11-25 13:11:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 锁存器
页数 文件大小 规格书
7页 226K
描述
Bus Driver, HC/UH Series, 1-Func, 8-Bit, Inverted Output, CMOS, PDIP20, PLASTIC, DIP-20

MC74HC563ND 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP,Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.92
其他特性:BROADSIDE VERSION OF 533系列:HC/UH
JESD-30 代码:R-PDIP-T20JESD-609代码:e0
长度:26.415 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):53 ns认证状态:Not Qualified
座面最大高度:4.57 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

MC74HC563ND 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
J SUFFIX  
CERAMIC PACKAGE  
CASE 732–03  
20  
20  
The MC54/74HC563 is identical in pinout to the LS563. The device inputs  
are compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
This device is identical in function to the HC533 but has the Data Inputs on  
the opposite side of the package from the outputs to facilitate PC board  
layout.  
These latches appear transparent to data (i.e., the outputs change  
asynchronously) when Latch Enable is high. The data appears at the outputs  
in inverted form. When Latch Enable goes low, data meeting the setup and  
hold time becomes latched.  
The Output Enable input does not affect the state of the latches, but when  
Output Enable is high, all device outputs are forced to the high–impedance  
state. Thus, data may be latched even when the outputs are not enabled.  
The HC573 is the noninverting version of this function.  
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
1
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
1
ORDERING INFORMATION  
MC54HCXXXJ  
MC74HCXXXN  
MC74HCXXXDW SOIC  
Ceramic  
Plastic  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
PIN ASSIGNMENT  
OUTPUT  
ENABLE  
1
20  
V
CC  
Chip Complexity: 202 FETs or 50.5 Equivalent Gates  
D0  
2
3
4
19  
18  
17  
Q0  
Q1  
Q2  
D1  
D2  
LOGIC DIAGRAM  
D3  
D4  
5
16  
15  
14  
13  
12  
11  
Q3  
Q4  
Q5  
Q6  
Q7  
19  
2
3
4
5
6
7
8
9
6
D0  
D1  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
18  
17  
16  
15  
14  
13  
12  
D5  
7
D6  
8
D2  
DATA  
INPUTS  
D3  
INVERTING  
OUTPUTS  
D7  
9
LATCH  
ENABLE  
D4  
GND  
10  
D5  
D6  
D7  
FUNCTION TABLE  
LATCH  
ENABLE  
11  
1
Inputs  
Output  
PIN 20 = V  
CC  
PIN 10 = GND  
OUTPUT  
ENABLE  
Output Latch  
Enable Enable  
D
Q
L
L
L
H
H
L
H
L
X
X
L
H
No Change  
Z
H
X
X = don’t care  
Z = high impedance  
10/95  
REV 6  
Motorola, Inc. 1995  

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