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MC74HC541DW PDF预览

MC74HC541DW

更新时间: 2024-02-26 02:02:29
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 驱动器
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6页 171K
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MC74HC541DW 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 732–03  
High–Performance Silicon–Gate CMOS  
The MC54/74HC541A is identical in pinout to the LS541. The device  
inputs are compatible with Standard CMOS outputs. External pullup  
resistors make them compatible with LSTTL outputs.  
The HC541A is an octal non–inverting buffer/line driver/line receiver  
designed to be used with 3–state memory address drivers, clock drivers, and  
other bus–oriented systems. This device features inputs and outputs on  
opposite sides of the package and two ANDed active–low output enables.  
The HC541A is similar in function to the HC540A, which has inverting  
outputs.  
20  
20  
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
1
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
1
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 2 to 6V  
ORDERING INFORMATION  
Low Input Current: 1µA  
MC54HCXXXAJ  
MC74HCXXXAN  
MC74HCXXXADW  
Ceramic  
Plastic  
SOIC  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance With the JEDEC Standard No. 7A Requirements  
Chip Complexity: 134 FETs or 33.5 Equivalent Gates  
LOGIC DIAGRAM  
FUNCTION TABLE  
Inputs  
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
Y8  
Output Y  
OE1 OE2  
A
L
L
L
L
L
H
X
X
L
H
Z
Z
H
X
X
H
Data  
Inputs  
Non–Inverting  
Outputs  
Z = High Impedance  
X = Don’t Care  
1
PIN 20 = V  
CC  
Output  
Enables  
OE1  
OE2  
PIN 10 = GND  
19  
Pinout: 20–Lead Packages (Top View)  
V
OE2  
19  
Y1  
18  
Y2  
17  
Y3  
16  
Y4  
15  
Y5  
14  
Y6  
13  
Y7  
12  
Y8  
11  
CC  
20  
1
2
3
4
5
6
7
9
8
10  
OE1  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
GND  
10/95  
Motorola, Inc. 1995  
REV 1  

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