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MC74HC541AN

更新时间: 2024-11-08 23:01:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
6页 171K
描述
Octal 3-State Non-Inverting Buffer/Line Driver/Line Receiver

MC74HC541AN 技术参数

生命周期:Transferred零件包装代码:DIP
包装说明:DIP, DIP20,.3针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.2Is Samacsys:N
其他特性:WITH DUAL OUTPUT ENABLE控制类型:ENABLE LOW
系列:HC/UHJESD-30 代码:R-PDIP-T20
JESD-609代码:e0长度:26.415 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.006 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:2/6 VProp。Delay @ Nom-Sup:28 ns
传播延迟(tpd):28 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

MC74HC541AN 数据手册

 浏览型号MC74HC541AN的Datasheet PDF文件第2页浏览型号MC74HC541AN的Datasheet PDF文件第3页浏览型号MC74HC541AN的Datasheet PDF文件第4页浏览型号MC74HC541AN的Datasheet PDF文件第5页浏览型号MC74HC541AN的Datasheet PDF文件第6页 
SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 732–03  
High–Performance Silicon–Gate CMOS  
The MC54/74HC541A is identical in pinout to the LS541. The device  
inputs are compatible with Standard CMOS outputs. External pullup  
resistors make them compatible with LSTTL outputs.  
The HC541A is an octal non–inverting buffer/line driver/line receiver  
designed to be used with 3–state memory address drivers, clock drivers, and  
other bus–oriented systems. This device features inputs and outputs on  
opposite sides of the package and two ANDed active–low output enables.  
The HC541A is similar in function to the HC540A, which has inverting  
outputs.  
20  
20  
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
1
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
1
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 2 to 6V  
ORDERING INFORMATION  
Low Input Current: 1µA  
MC54HCXXXAJ  
MC74HCXXXAN  
MC74HCXXXADW  
Ceramic  
Plastic  
SOIC  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance With the JEDEC Standard No. 7A Requirements  
Chip Complexity: 134 FETs or 33.5 Equivalent Gates  
LOGIC DIAGRAM  
FUNCTION TABLE  
Inputs  
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
Y8  
Output Y  
OE1 OE2  
A
L
L
L
L
L
H
X
X
L
H
Z
Z
H
X
X
H
Data  
Inputs  
Non–Inverting  
Outputs  
Z = High Impedance  
X = Don’t Care  
1
PIN 20 = V  
CC  
Output  
Enables  
OE1  
OE2  
PIN 10 = GND  
19  
Pinout: 20–Lead Packages (Top View)  
V
OE2  
19  
Y1  
18  
Y2  
17  
Y3  
16  
Y4  
15  
Y5  
14  
Y6  
13  
Y7  
12  
Y8  
11  
CC  
20  
1
2
3
4
5
6
7
9
8
10  
OE1  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
GND  
10/95  
Motorola, Inc. 1995  
REV 1  

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