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MC74HC51DS PDF预览

MC74HC51DS

更新时间: 2024-11-04 13:11:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA
页数 文件大小 规格书
4页 150K
描述
AND-OR-Invert Gate, CMOS, PDSO14

MC74HC51DS 技术参数

是否Rohs认证:不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.92
Is Samacsys:NJESD-30 代码:R-PDSO-G14
JESD-609代码:e0逻辑集成电路类型:AND-OR-INVERT GATE
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:2/6 V认证状态:Not Qualified
施密特触发器:NO子类别:Gates
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

MC74HC51DS 数据手册

 浏览型号MC74HC51DS的Datasheet PDF文件第2页浏览型号MC74HC51DS的Datasheet PDF文件第3页浏览型号MC74HC51DS的Datasheet PDF文件第4页 
SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
N SUFFIX  
PLASTIC PACKAGE  
CASE 646–06  
14  
The MC74HC51 is identical in pinout to the LS51. The device inputs are  
compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
1
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
D SUFFIX  
SOIC PACKAGE  
CASE 751A–03  
14  
1
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
ORDERING INFORMATION  
MC74HCXXN  
MC74HCXXD  
Plastic  
SOIC  
Chip Complexity: 42 FETs or 10.5 Equivalent Gates  
PIN ASSIGNMENT  
A1  
A2  
1
2
14  
13  
V
CC  
LOGIC DIAGRAM  
C1  
1
B2  
C2  
3
4
12  
11  
B1  
F1  
A1  
12  
B1  
13  
D2  
Y2  
5
6
10  
9
E1  
D1  
C1  
D1  
E1  
F1  
8
Y1  
9
10  
11  
Y1 = (A1B1C1) + (D1E1F1)  
GND  
7
8
Y1  
2
3
A2  
B2  
FUNCTION TABLES  
Inputs  
6
Y2  
Output  
Y1  
4
5
Y2 = (A2B2) + (C2D2)  
C2  
D2  
A1 B1 C1 D1 E1 F1  
H
X
H
X
H
X
X
H
X
H
X
H
L
L
All other combinations  
H
PIN 14 = V  
CC  
PIN 7 = GND  
Inputs  
Output  
Y2  
A2  
B2  
C2  
D2  
H
X
H
X
X
H
X
H
L
L
All other combinations  
H
10/95  
REV 6  
Motorola, Inc. 1995  

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