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MC74HC4316N

更新时间： 2024-11-11 23:01:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 解复用器开关复用器或开关信号电路
页数 文件大小 规格书
10页 350K
描述
Quad Analog Switch/Multiplexer/Demultiplexer with Separate Analog and Digital Power Supplies

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中文翻译

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MC74HC4316N 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：PLASTIC, DIP-16Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.6
Is Samacsys：N模拟集成电路 - 其他类型：SPST
JESD-30 代码：R-PDIP-T16JESD-609代码：e0
长度：19.175 mm标称负供电电压 (Vsup)：-6 V
信道数量：1功能数量：4
端子数量：16标称断态隔离度：40 dB
通态电阻匹配规范：20 Ω最大通态电阻 (Ron)：90 Ω
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
认证状态：Not Qualified座面最大高度：4.44 mm
最大供电电流 (Isup)：0.16 mA最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：6 V
表面贴装：NO最长断开时间：15 ns
最长接通时间：15 ns技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

MC74HC4316N 数据手册

 浏览型号MC74HC4316N的Datasheet PDF文件第2页浏览型号MC74HC4316N的Datasheet PDF文件第3页浏览型号MC74HC4316N的Datasheet PDF文件第4页浏览型号MC74HC4316N的Datasheet PDF文件第5页浏览型号MC74HC4316N的Datasheet PDF文件第6页浏览型号MC74HC4316N的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
1
High–Performance Silicon–Gate CMOS  
The MC74HC4316 utilizes silicon–gate CMOS technology to achieve fast  
propagation delays, low ON resistances, and low OFF–channel leakage  
current. This bilateral switch/multiplexer/demultiplexer controls analog and  
digital voltages that may vary across the full analog power–supply range  
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
1
(from V  
to V ).  
CC  
EE  
ORDERING INFORMATION  
The HC4316 is similar in function to the metal–gate CMOS MC14016 and  
MC14066, and to the High–Speed CMOS HC4016 and HC4066. Each  
device has four independent switches. The device control and Enable inputs  
are compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs. The device has been designed so that the  
MC74HCXXXXN  
MC74HCXXXXD  
Plastic  
SOIC  
ON resistances (R ) are much more linear over input voltage than R  
metal–gate CMOS analog switches. Logic–level translators are provided so  
that the On/Off Control and Enable logic–level voltages need only be V  
of  
ON  
ON  
PIN ASSIGNMENT  
CC  
X
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
CC  
A
and GND, while the switch is passing signals ranging between V  
When the Enable pin (active–low) is high, all four analog switches are turned  
off.  
and V  
.
CC  
EE  
A ON/OFF  
CONTROL  
Y
A
D ON/OFF  
CONTROL  
Y
B
B
•
•
•
•
•
•
Logic–Level Translator for On/Off Control and Enable Inputs  
Fast Switching and Propagation Speeds  
High ON/OFF Output Voltage Ratio  
X
X
Y
Y
X
V
D
B ON/OFF  
CONTROL  
C ON/OFF  
CONTROL  
ENABLE  
D
C
Diode Protection on All Inputs/Outputs  
C
Analog Power–Supply Voltage Range (V  
CC  
– V ) = 2.0 to 12.0 Volts  
EE  
Digital (Control) Power–Supply Voltage Range (V  
6.0 Volts, Independent of V  
EE  
– GND) = 2.0 to  
GND  
CC  
EE  
•
•
Improved Linearity of ON Resistance  
Chip Complexity: 66 FETs or 16.5 Equivalent Gates  
FUNCTION TABLE  
LOGIC DIAGRAM  
Inputs  
State of  
Analog  
Switch  
On/Off  
Enable  
Control  
1
ANALOG  
SWITCH  
2
3
X
Y
A
A
L
L
H
H
L
X
On  
Off  
Off  
15  
A ON/OFF CONTROL  
LEVEL  
TRANSLATOR  
X = don’t care  
4
5
ANALOG  
SWITCH  
X
Y
Y
Y
B
B
C
D
ANALOG  
OUTPUTS/INPUTS  
B ON/OFF CONTROL  
LEVEL  
TRANSLATOR  
10  
6
ANALOG  
SWITCH  
11  
12  
X
C
PIN 16 = V  
CC  
PIN 8 = GND  
PIN 9 = V  
C ON/OFF CONTROL  
LEVEL  
TRANSLATOR  
EE  
EE  
GND  
≥ V  
13  
ANALOG  
SWITCH  
X
D
14  
7
D ON/OFF CONTROL  
ENABLE  
LEVEL  
TRANSLATOR  
ANALOG INPUTS/OUTPUTS = X , X , X , X  
D
A
B
C
10/95  
Motorola, Inc. 1995  
REV 6  
1234567...10

中文翻译

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