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MC74HC244ADTR2 PDF预览

MC74HC244ADTR2

更新时间: 2024-10-27 22:39:07
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 183K
描述
Octal 3-State Noninverting Buffer/Line Driver/Line Receiver

MC74HC244ADTR2 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:LEAD FREE, TSSOP-20
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.35
Is Samacsys:N控制类型:ENABLE LOW
系列:HC/UHJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:6.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.006 A湿度敏感等级:1
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:2/6 V
Prop。Delay @ Nom-Sup:27 ns传播延迟(tpd):135 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:4.4 mmBase Number Matches:1

MC74HC244ADTR2 数据手册

 浏览型号MC74HC244ADTR2的Datasheet PDF文件第2页浏览型号MC74HC244ADTR2的Datasheet PDF文件第3页浏览型号MC74HC244ADTR2的Datasheet PDF文件第4页浏览型号MC74HC244ADTR2的Datasheet PDF文件第5页浏览型号MC74HC244ADTR2的Datasheet PDF文件第6页浏览型号MC74HC244ADTR2的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74HC244A is identical in pinout to the LS244. The device  
inputs are compatible with standard CMOS outputs; with pullup  
resistors, they are compatible with LSTTL outputs.  
This octal noninverting buffer/line driver/line receiver is designed  
to be used with 3–state memory address drivers, clock drivers, and  
other bus–oriented systems. The device has noninverting outputs and  
two active–low output enables.  
http://onsemi.com  
MARKING  
DIAGRAMS  
20  
PDIP–20  
N SUFFIX  
CASE 738  
MC74HC244AN  
AWLYYWW  
The HC244A is similar in function to the HC240A.  
20  
1
1
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
20  
SOIC WIDE–20  
DW SUFFIX  
CASE 751D  
HC244A  
AWLYYWW  
20  
1
1
20  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
HC  
244A  
ALYW  
TSSOP–20  
DT SUFFIX  
CASE 948G  
20  
1
Chip Complexity: 136 FETs or 34 Equivalent Gates  
1
LOGIC DIAGRAM  
A
= Assembly Location  
2
4
6
8
18  
16  
14  
12  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
A1  
A2  
A3  
A4  
YA1  
YA2  
YA3  
YA4  
PIN ASSIGNMENT  
ENABLE A  
A1  
1
2
3
4
5
6
7
8
9
20  
V
CC  
19 ENABLE B  
18 YA1  
17 B4  
DATA  
INPUTS  
NONINVERTING  
OUTPUTS  
YB4  
A2  
11  
13  
15  
17  
9
7
5
3
B1  
B2  
B3  
B4  
YB1  
YB2  
YB3  
YB4  
YB3  
A3  
16 YA2  
15 B3  
YB2  
A4  
14 YA3  
13 B2  
YB1  
12 YA4  
11 B1  
GND 10  
PIN 20 = V  
CC  
PIN 10 = GND  
1
ENABLE A  
ENABLE B  
OUTPUT  
ENABLES  
19  
ORDERING INFORMATION  
FUNCTION TABLE  
Device  
Package  
PDIP–20  
Shipping  
Inputs  
Enable A,  
Enable B A, B  
Outputs  
MC74HC244AN  
1440 / Box  
38 / Rail  
YA, YB  
MC74HC244ADW  
MC74HC244ADWR2  
MC74HC244ADT  
MC74HC244ADTR2  
SOIC–WIDE  
L
L
H
L
H
X
L
H
Z
SOIC–WIDE 1000 / Reel  
TSSOP–20 75 / Rail  
Z = high impedance  
TSSOP–20 2500 / Reel  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 8  
MC74HC244A/D  

MC74HC244ADTR2 替代型号

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