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MC74HC132ADG PDF预览

MC74HC132ADG

更新时间: 2024-01-20 18:08:47
品牌 Logo 应用领域
安森美 - ONSEMI 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
10页 116K
描述
Quad 2−Input NAND Gate with Schmitt−Trigger Inputs High−Performance Silicon−Gate CMOS

MC74HC132ADG 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP14,.3Reach Compliance Code:unknown
风险等级:5.58JESD-30 代码:R-PDIP-T14
JESD-609代码:e0逻辑集成电路类型:NAND GATE
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:2/6 V认证状态:Not Qualified
施密特触发器:YES子类别:Gates
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

MC74HC132ADG 数据手册

 浏览型号MC74HC132ADG的Datasheet PDF文件第2页浏览型号MC74HC132ADG的Datasheet PDF文件第3页浏览型号MC74HC132ADG的Datasheet PDF文件第4页浏览型号MC74HC132ADG的Datasheet PDF文件第5页浏览型号MC74HC132ADG的Datasheet PDF文件第6页浏览型号MC74HC132ADG的Datasheet PDF文件第7页 
MC74HC132A  
Quad 2−Input NAND Gate  
with Schmitt−Trigger Inputs  
High−Performance Silicon−Gate CMOS  
The MC74HC132A is identical in pinout to the LS132. The device  
inputs are compatible with standard CMOS outputs; with pull−up  
resistors, they are compatible with LSTTL outputs.  
The HC132A can be used to enhance noise immunity or to square up  
slowly changing waveforms.  
http://onsemi.com  
MARKING  
DIAGRAMS  
14  
Features  
PDIP−14  
N SUFFIX  
CASE 646  
MC74HC132AN  
AWLYYWWG  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 mA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements as Defined by JEDEC  
Standard No. 7A  
1
14  
SOIC−14  
D SUFFIX  
CASE 751A  
HC132AG  
AWLYWW  
1
Chip Complexity: 72 FETs or 18 Equivalent Gates  
Pb−Free Packages are Available  
14  
HC  
132A  
ALYWG  
G
TSSOP−14  
DT SUFFIX  
CASE 948G  
A1  
B1  
1
2
14  
13 B4  
12  
V
CC  
1
14  
Y1  
A2  
3
4
A4  
SOEIAJ−14  
F SUFFIX  
CASE 965  
11 Y4  
10 B3  
74HC132A  
ALYWG  
B2  
Y2  
5
6
9
8
A3  
Y3  
1
GND  
7
A
= Assembly Location  
L, WL = Wafer Lot  
Y, YY = Year  
Figure 1. Pin Assignment  
W, WW = Work Week  
G or G = Pb−Free Package  
(Note: Microdot may be in either location)  
FUNCTION TABLE  
Inputs  
Output  
Y
A
B
L
L
H
H
L
H
L
H
H
H
L
H
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 − Rev. 12  
MC74HC132A/D  

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