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MC74HC10

更新时间： 2024-02-04 21:50:33

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		栅
页数	文件大小	规格书
4页	141K
描述
Triple 3-Input NAND Gate

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中文翻译

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技术参数
数据手册

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MC74HC10 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.68	逻辑集成电路类型：	AND GATE
Base Number Matches：	1

MC74HC10 数据手册

SEMICONDUCTOR TECHNICAL DATA

High–Performance Silicon–Gate CMOS

N SUFFIX

PLASTIC PACKAGE

CASE 646–06

The MC74HC10 is identical in pinout to the LS10. The device inputs are

compatible with standard CMOS outputs; with pullup resistors, they are

compatible with LSTTL outputs.

•

Output Drive Capability: 10 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 2 to 6 V

D SUFFIX

SOIC PACKAGE

CASE 751A–03

Low Input Current: 1 µA

High Noise Immunity Characteristic of CMOS Devices

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

ORDERING INFORMATION

•

Chip Complexity: 36 FETs or 9 Equivalent Gates

MC74HCXXN

MC74HCXXD

Plastic

SOIC

LOGIC DIAGRAM

PIN ASSIGNMENT

Y = ABC

GND

FUNCTION TABLE

Inputs

PIN 14 = V

PIN 7 = GND

Output

10/95

REV 6

Motorola, Inc. 1995

12 3 4

中文翻译

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与MC74HC10相关器件

型号	品牌	获取价格	描述	数据表
MC74HC107	MOTOROLA	获取价格	Dual J-K Flip-Flop with Reset
MC74HC107D	MOTOROLA	获取价格	Dual J-K Flip-Flop with Reset
MC74HC107DD	MOTOROLA	获取价格	暂无描述
MC74HC107DR2	MOTOROLA	获取价格	J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output,
MC74HC107N	MOTOROLA	获取价格	Dual J-K Flip-Flop with Reset
MC74HC107ND	MOTOROLA	获取价格	暂无描述
MC74HC107NS	MOTOROLA	获取价格	暂无描述
MC74HC109D	MOTOROLA	获取价格	Dual J-K Flip-Flop with Set and Reset
MC74HC109DDR2	MOTOROLA	获取价格	HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16,
MC74HC109DDS	MOTOROLA	获取价格	J-K Flip-Flop, 2-Func, Positive Edge Triggered, CMOS, PDSO16