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MC74HC03AN PDF预览

MC74HC03AN

更新时间: 2024-11-17 23:01:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 178K
描述
Quad 2-Input NAND Gate With Open-Drain Outputs

MC74HC03AN 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:PLASTIC, DIP-14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.73
系列:HC/UHJESD-30 代码:R-PDIP-T14
JESD-609代码:e0长度:18.86 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.004 A功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:OPEN-DRAIN封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:2/6 VProp。Delay @ Nom-Sup:36 ns
传播延迟(tpd):36 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:4.69 mm
子类别:Gates最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

MC74HC03AN 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
N SUFFIX  
PLASTIC PACKAGE  
CASE 646–06  
The MC74HC03A is identical in pinout to the LS03. The device inputs  
are compatible with Standard CMOS outputs; with pullup resistors, they  
are compatible with LSTTL outputs.  
14  
1
The HC03A NAND gate has, as its outputs, a high–performance MOS  
N–Channel transistor. This NAND gate can, therefore, with a suitable  
pullup resistor, be used in wired–AND applications. Having the output  
characteristic curves given in this data sheet, this device can be used as  
an LED driver or in any other application that only requires a sinking  
current.  
D SUFFIX  
SOIC PACKAGE  
CASE 751A–03  
14  
1
DT SUFFIX  
TSSOP PACKAGE  
CASE 948G–01  
14  
Output Drive Capability: 10 LSTTL Loads With Suitable Pullup Resistor  
Outputs Directly Interface to CMOS, NMOS and TTL  
High Noise Immunity Characteristic of CMOS Devices  
Operating Voltage Range: 2 to 6V  
Low Input Current: 1µA  
In Compliance With the JEDEC Standard No. 7A Requirements  
Chip Complexity: 28 FETs or 7 Equivalent Gates  
1
ORDERING INFORMATION  
MC74HCXXAN  
MC74HCXXAD  
MC74HCXXADT  
Plastic  
SOIC  
TSSOP  
DESIGN GUIDE  
FUNCTION TABLE  
Criteria  
Value  
7.0  
Unit  
ea  
Inputs  
Output  
Internal Gate Count*  
A
B
Y
Internal Gate Propagation Delay  
Internal Gate Power Dissipation  
1.5  
ns  
5.0  
µW  
pJ  
L
L
L
H
L
Z
Z
Z
L
Speed Power Product  
0.0075  
H
H
* Equivalent to a two–input NAND gate  
H
Z = High Impedance  
LOGIC DIAGRAM  
V
CC  
Pinout: 14–Lead Packages (Top View)  
OUTPUT  
PROTECTION  
DIODE  
V
B4  
13  
A4  
12  
Y4  
11  
B3  
10  
A3  
9
Y3  
8
CC  
3,6,8,11  
Y*  
14  
1,4,9,12  
A
2,5,10,13  
B
PIN 14 = V  
CC  
1
2
3
4
5
6
7
PIN 7 = GND  
* Denotes open–drain outputs  
A1  
B1  
Y1  
A2  
B2  
Y2  
GND  
10/95  
Motorola, Inc. 1995  
REV 7  

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