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MC74HC03ADT PDF预览

MC74HC03ADT

更新时间: 2024-11-03 23:01:35
品牌 Logo 应用领域
安森美 - ONSEMI 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 155K
描述
Quad 2-Input NAND Gate with Open-Drain Outputs

MC74HC03ADT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP14,.25
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.5系列:HC/UH
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE最大I(ol):0.004 A
湿度敏感等级:1功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:OPEN-DRAIN封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
Prop。Delay @ Nom-Sup:36 ns传播延迟(tpd):180 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.2 mm子类别:Gates
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

MC74HC03ADT 数据手册

 浏览型号MC74HC03ADT的Datasheet PDF文件第2页浏览型号MC74HC03ADT的Datasheet PDF文件第3页浏览型号MC74HC03ADT的Datasheet PDF文件第4页浏览型号MC74HC03ADT的Datasheet PDF文件第5页浏览型号MC74HC03ADT的Datasheet PDF文件第6页浏览型号MC74HC03ADT的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74HC03A is identical in pinout to the LS03. The device  
inputs are compatible with Standard CMOS outputs; with pullup  
resistors, they are compatible with LSTTL outputs.  
http://onsemi.com  
The HC03A NAND gate has, as its outputs, a high–performance  
MOS N–Channel transistor. This NAND gate can, therefore, with a  
suitable pullup resistor, be used in wired–AND applications. Having  
the output characteristic curves given in this data sheet, this device can  
be used as an LED driver or in any other application that only requires  
a sinking current.  
MARKING  
DIAGRAMS  
14  
PDIP–14  
N SUFFIX  
CASE 646  
MC74HC03AN  
AWLYYWW  
1
Output Drive Capability: 10 LSTTL Loads With Suitable Pullup  
Resistor  
14  
SOIC–14  
D SUFFIX  
CASE 751A  
HC03A  
AWLYWW  
Outputs Directly Interface to CMOS, NMOS and TTL  
High Noise Immunity Characteristic of CMOS Devices  
Operating Voltage Range: 2 to 6V  
Low Input Current: 1µA  
In Compliance With the JEDEC Standard No. 7A Requirements  
Chip Complexity: 28 FETs or 7 Equivalent Gates  
DESIGN GUIDE  
1
14  
HC  
03A  
ALYW  
TSSOP–14  
DT SUFFIX  
CASE 948G  
1
A
= Assembly Location  
Criteria  
Value  
7.0  
Unit  
ea  
WL or L = Wafer Lot  
YY or Y = Year  
Internal Gate Count*  
WW or W = Work Week  
Internal Gate Propagation Delay  
Internal Gate Power Dissipation  
Speed Power Product  
1.5  
ns  
5.0  
µW  
pJ  
FUNCTION TABLE  
0.0075  
Inputs  
Output  
* Equivalent to a two–input NAND gate  
LOGIC DIAGRAM  
A
B
Y
V
CC  
L
L
L
H
L
Z
Z
Z
L
OUTPUT  
PROTECTION  
DIODE  
PIN 14 = V  
PIN 7 = GND  
* Denotes open–drain outputs  
CC  
H
H
H
3,6,8,11  
Y*  
Z = High Impedance  
1,4,9,12  
A
2,5,10,13  
B
ORDERING INFORMATION  
Pinout: 14–Lead Packages (Top View)  
Device  
Package  
PDIP–14  
Shipping  
V
14  
B4  
13  
A4  
12  
Y4  
11  
B3  
10  
A3  
9
Y3  
8
CC  
MC74HC03AN  
2000 / Box  
55 / Rail  
MC74HC03AD  
SOIC–14  
SOIC–14  
TSSOP–14  
TSSOP–14  
MC74HC03ADR2  
MC74HC03ADT  
MC74HC03ADTR2  
2500 / Reel  
96 / Rail  
1
2
3
4
5
6
7
2500 / Reel  
A1  
B1  
Y1  
A2  
B2  
Y2 GND  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 8  
MC74HC03A/D  

MC74HC03ADT 替代型号

型号 品牌 替代类型 描述 数据表
MC74HC03ADTEL ONSEMI

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