MC74HC00A
Quad 2−Input NAND Gate
High−Performance Silicon−Gate CMOS
The MC74HC00A is identical in pinout to the LS00. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
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Features
MARKING
DIAGRAMS
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2 to 6 V
14
1
PDIP−14
N SUFFIX
CASE 646
• Low Input Current: 1 mA
MC74HC00AN
AWLYYWWG
14
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7 A Requirements
• Chip Complexity: 32 FETs or 8 Equivalent Gates
• Pb−Free Packages are Available
1
14
SOIC−14
D SUFFIX
HC00AG
AWLYWW
14
CASE 751A
1
LOGIC DIAGRAM
1
1
A1
3
Y1
2
B1
14
TSSOP−14
DT SUFFIX
CASE 948G
4
HC
00A
ALYW
ꢀ
14
A2
6
Y2
5
ꢀ
1
B2
Y = AB
9
1
A3
8
Y3
10
B3
12
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
A4
11
Y4
13
B4
WW or W = Work Week
G or
ꢀ
= Pb−Free Package
PIN 14 = V
CC
PIN 7 = GND
(Note: Microdot may be in either location)
Pinout: 14−Lead Packages (Top View)
V
CC
B4
A4
Y4
B3
A3
Y3
FUNCTION TABLE
14
13
12
11
10
9
8
Inputs
Output
Y
A
B
L
L
L
H
L
H
H
H
L
H
H
H
1
2
3
4
5
6
7
A1
B1
Y1
A2
B2
Y2 GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
October, 2006 − Rev. 11
MC74HC00A/D