MC54/74F539
DUAL 1-OF-4 DECODER
WITH 3-STATE OUTPUTS
The MC54/74F539 contains two independent decoders. Each accepts two
Address (A –A ) input signals and decodes them to select one of four
0
1
DUAL 1-OF-4 DECODER
WITH 3-STATE OUTPUTS
mutuallyexclusiveoutputs. Apolaritycontrolinput(P)determineswhetherthe
outputs are active HIGH (P = L) or active LOW (P = H). An active LOW input
Enable (E) is available for data demultiplexing; data is routed to the selected
output in non-inverted form in the active LOW mode or in inverted form in the
active HIGH mode. A HIGH Signal on the active LOW Output Enable (OE)
input forces the 3-state outputs to the high impedance state.
FAST SCHOTTKY TTL
• Demultiplexing Capability
• 3-State Outputs
• Two Completely Independent 1-of-4 Decoders
• Input Clamp Diodes Limit High Speed Termination Effects
• ESD Protection > 4000 Volts
J SUFFIX
CERAMIC
CASE 732-03
20
CONNECTION DIAGRAM DIP (TOP VIEW)
1
V
O
A
A
E
E
OE
P
O
O
1a
CC
20
3b
19
1b
18
0b
17
b
a
a
a
0a
12
16
15
14
13
11
N SUFFIX
PLASTIC
CASE 738-03
20
1
DW SUFFIX
SOIC
CASE 751D-03
1
2
3
4
5
6
8
9
10
7
20
O
O
O
P
OE
A
A
O
O GND
2a
2b
1b
0b
b
b
0a
1a
3a
1
LOGIC DIAGRAM (1/2 SHOWN)
A
A
1
ORDERING INFORMATION
MC54FXXXJ
MC74FXXXN
Ceramic
Plastic
0
MC74FXXXDW SOIC
E
P
LOGIC SYMBOL
13
6
7
P
A
A
1
0
15
14
E
DECODER a
OE
O
O
O
O
0
1
2 3
12 11
9
8
V
= PIN 20
CC
GND = PIN 10
4
17 18
P
A
A
0 1
OE
16
5
E
DECODER b
O
O
O
O
3
OE
0
1
2
O
O
O
O
0
1
2
3
19
Please note that this diagram is provided only for the understanding of logic operations and
should not be used to estimate propagation delays.
3
2
1
FAST AND LS TTL DATA
4-209