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MC74ACT373DWC PDF预览

MC74ACT373DWC

更新时间: 2024-02-08 01:24:38
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 锁存器输出元件
页数 文件大小 规格书
8页 202K
描述
ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, SOIC-20

MC74ACT373DWC 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DIP
包装说明:LEAD FREE, PLASTIC, DIP-8针数:8
Reach Compliance Code:unknownHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5
Is Samacsys:N系列:ACT
JESD-30 代码:R-PDIP-T20JESD-609代码:e3
长度:26.415 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):260
电源:5 VProp。Delay @ Nom-Sup:11.5 ns
传播延迟(tpd):11.5 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:7.62 mm
Base Number Matches:1

MC74ACT373DWC 数据手册

 浏览型号MC74ACT373DWC的Datasheet PDF文件第2页浏览型号MC74ACT373DWC的Datasheet PDF文件第3页浏览型号MC74ACT373DWC的Datasheet PDF文件第4页浏览型号MC74ACT373DWC的Datasheet PDF文件第5页浏览型号MC74ACT373DWC的Datasheet PDF文件第6页浏览型号MC74ACT373DWC的Datasheet PDF文件第7页 
OCTAL TRANSPARENT  
LATCH WITH  
3-STATE OUTPUTS  
The MC74AC373/74ACT373 consists of eight latches with 3-state outputs for bus  
organized system applications. The flip-flops appear transparent to the data when  
Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is  
latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE  
is HIGH, the bus output is in the high impedance state.  
Eight Latches in a Single Package  
3-State Outputs for Bus Interfacing  
Outputs Source/Sink 24 mA  
• ′ACT373 Has TTL Compatible Inputs  
N SUFFIX  
CASE 738-03  
PLASTIC  
V
O
D
D
O
O
D
D
O
4
LE  
11  
CC  
7
7
6
6
5
5
4
20  
19  
18  
17  
16  
15  
14  
12  
13  
DW SUFFIX  
CASE 751D-04  
PLASTIC  
1
2
3
4
5
6
7
9
8
10  
OE  
O
D
D
O
O
D
D
O
3
GND  
0
0
1
1
2
2
3
PIN NAMES  
LOGIC SYMBOL  
D –D  
0
Data Inputs  
Latch Enable Input  
Output Enable Input  
7
LE  
OE  
D
O
D
O
D
O
D
O
D
O
D
O
D
O
D
O
0
1
2
3
4
5
6
7
O –O  
3-State Latch Outputs  
LE  
0
7
OE  
0
1
2
3
4
5
6
7
TRUTH TABLE  
Inputs  
Outputs  
OE  
LE  
D
O
n
n
H
L
L
L
X
H
H
L
X
Z
L
H
L
H
X
O
0
H = HIGH Voltage Level  
L = LOW Voltage Level  
Z = High Impedance  
X = Immaterial  
O
= Previous O before LOW-to-HIGH Transition of Clock  
0
0
FACT DATA  
5-1  

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