Order Number: MC68HC55
Rev. 2
MC68HC55/D
Technical Data
Two-Channel CMOS ASIC Device
Section 1. DSI/D (Distributed System Interface – Digital)
1.1
1.2
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
General Description of the DSI System. . . . . . . . . . . . . . . . .3
Overall DSI System Connections . . . . . . . . . . . . . . . . . . . . .3
Section 2. MC68HC55CD Pin Assignments and Descriptions
2.1
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.2
Pin Function Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Section 3. Registers and Bit Descriptions
3.1
3.2
3.3
3.4
3.5
DSI Channel 0 Data Registers . . . . . . . . . . . . . . . . . . . . . . .9
DSI Channel 1 Data Registers . . . . . . . . . . . . . . . . . . . . . .10
DSI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
DSI Channel Control Registers . . . . . . . . . . . . . . . . . . . . . .13
DSI Channel Enable Bits. . . . . . . . . . . . . . . . . . . . . . . . . . .17
Section 4. Functional Description
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Abort Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Enable (Disable) Function. . . . . . . . . . . . . . . . . . . . . . . . . .20
SPI Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
DSI/D to DSI/P Communications. . . . . . . . . . . . . . . . . . . . .29
CRC Generation/Checking . . . . . . . . . . . . . . . . . . . . . . . . .30
CRC Computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Message Size Special Cases . . . . . . . . . . . . . . . . . . . . . . .31
Section 5. Timing and Electrical Specifications
5.1
5.2
5.3
5.4
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . .34
Timing Characteristics for DSI/D to DSI/P Interface . . . . . .34
Timing Characteristics for SPI Interface . . . . . . . . . . . . . . .36
Section 6. Mechanical Data and Ordering Information
6.1
6.2
6.3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 1999, 2006