Datasheet > MC68150FN40R2

MC68150FN40R2

更新时间： 2024-11-03 21:11:59

品牌	Logo	应用领域
艾迪悌 - IDT		外围集成电路
页数	文件大小	规格书
40页	875K
描述
Microprocessor Circuit, PQCC68

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MC68150FN40R2 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	not_compliant	风险等级：	5.9
JESD-30 代码：	S-PQCC-J68	JESD-609代码：	e0
湿度敏感等级：	1	端子数量：	68
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC68,1.0SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	电源：	5 V
认证状态：	Not Qualified	子类别：	Other Microprocessor ICs
最大压摆率：	0.1 mA	标称供电电压：	5 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT	Base Number Matches：	1

MC68150FN40R2 数据手册

M OT O R OL A

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MC68150/D

Freescale Semiconductor, Inc.

DATA SHEET

Siz e r

MC68150

32-Bit to 32/16/8-Bit Dynamic

READ/WRITE Bus Sizer

The MC68150 Dynamic Bus Sizer is designed to allow the 32-bit

MC68/LC/EC040 bus, or other 16- to 32-bit processors, to communicate

bi-directionally with 32-, 16-, or 8-bit peripherals and memories. It

dynamically recognizes the size of the selected peripheral/memory and

then writes or reads the appropriate data to or from that location. Systems

designed using the bus sizing feature built into the 68030 can now be

easily upgraded to the 68/EC040 by incorporating the MC68150. The

68150 comes in two speed grades: 25/33MHz and 40MHz. These

frequencies correspond to their 68040 counterparts. The two grades

should be ordered as the MC68150FN33 and MC68150FN40,

respectively.

DYNAMIC

READ/WRITE

BUS SIZER

Typical operations which call for bus sizing are booting up instructions

from 8-bit ROM (EPROM, EEPROM, etc.) and communicating with 8-bit

SRAM’s for scratch pad memory storage during interrupt operations. The

dynamic property is necessary because the processor does not always

know the size of the peripheral it is accessing, as in the case of

communicating with a 16-bit VME bus. The MC68150 can also be used to

separate a 32-bit “Fast Bus” and an 8-, 16-, or 32-bit “Slow Bus”. (See

Figure 3)

Features

• Allows MC68/LC/EC040 or Other ‘040 Based Controllers or 68060 to

Communicate With 8-Bit Memories and Any MC68XXX Peripheral

• Also Allows Other RISC Processors to Communicate With 8-Bit and

FN SUFFIX

PLASTIC PACKAGE

CASE 779-02

16-Bit Peripherals

• Recognizes the Port (Peripheral) Size Dynamically

• Generates Byte/Word Address to the Dynamic Port

• Generates Byte WRITE Enable Signals For 16- and 8-bit Ports

• Sends a Transfer Acknowledge Signal to the Processor When a

Transfer Is Completed

• Synchronization of Data Transfer on Dynamic Port Allows Use of Any

Speed Peripheral

1. Overview of Chip Operation

Each access through the MC68150 is started with a chip select (CS) assertion to the MC68150 - which is generated when a

PAL sees a TS signal from the ‘040 - and completed with a transfer acknowledge (TA) from the MC68150 to the MC68040. The

MC68150 has two distinct buses, the MPU bus and the peripheral bus. The MPU bus connects to the processor and includes the

transfer control signals (A1, A0, SIZ1, SIZ0, and R/W), the chip select (CS), the transfer acknowledge (TA) and the data bus

signals (D31-D0). The peripheral bus consists of the peripheral transfer control signals (SWE, UWE, LWE, DS, PA1, PA0), and

the peripheral transfer acknowledge signals (DSACK1, DSACK0) and the peripheral data bus (PD31-PD16).

If a 32-bit peripheral bus is used, then two additional transceivers (e.g. MC74F245) are required for the lower two bytes of the

data. These transceivers would be connected to the PD15-PD0 pins on the peripheral side and to the corresponding D15-D0 pins

on the MPU bus. The transfer direction is controlled with the R/W signal of the processor. The transceivers are enabled only when

making an access to a 32-bit port. The D15-D0 pins of the MPU bus on the MC68150 are always disabled until the port size is

known, to avoid bus contention when the port is 32-bits.

An access refers to the complete transaction through the MC68150. On the peripheral bus, an access is split into one, two, or

four separate transfers.

IDT™ 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer

MC68150

11/94

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

REV 4

Motorola, Inc. 1994

For More Informati¹on On This Product,

Go to: www.freescale.com

12 3 4 5 6 7...40

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与MC68150FN40R2相关器件

型号	品牌	获取价格	描述	数据表
MC68153	MOTOROLA	获取价格	BUS INTERRUPTER MODULE
MC68153	FREESCALE	获取价格	BUS INTERRUPTER MODULE
MC68153L	MOTOROLA	获取价格	暂无描述
MC68153P	MOTOROLA	获取价格	Microprocessor Circuit, CMOS, PDIP40, DIP-40
MC68160	MOTOROLA	获取价格	ENHANCED ETHERNET INTERFACE TRANSCEIVER
MC68160A	MOTOROLA	获取价格	ENHANCED ETHERNET INTERFACE TRANSCEIVER
MC68160A	IDT	获取价格	Enhanced Ethernet Transceiver
MC68160AEB	IDT	获取价格	Ethernet Transceiver, 1-Trnsvr, BICMOS, PQFP52, PLASTIC, LQFP-52
MC68160AEBR2	IDT	获取价格	Ethernet Transceiver, 1-Trnsvr, BICMOS, PQFP52
MC68160AFB	IDT	获取价格	Enhanced Ethernet Transceiver

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