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MC56F82316VLHR PDF预览

MC56F82316VLHR

更新时间： 2024-09-17 04:28:55
品牌 Logo 应用领域
恩智浦 - NXP 时钟微控制器外围集成电路
页数 文件大小 规格书
68页 1083K
描述
Microcontroller

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中文翻译

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MC56F82316VLHR 技术参数

生命周期：Active包装说明：QFP,
Reach Compliance Code：unknownHTS代码：8542.31.00.01
风险等级：5.78具有ADC：YES
地址总线宽度：位大小：32
最大时钟频率：16 MHzDMA 通道：YES
外部数据总线宽度：长度：7 mm
I/O 线路数量：39端子数量：48
PWM 通道：YES封装代码：QFP
封装形状：SQUARE封装形式：FLATPACK
速度：50 MHz最大供电电压：3.6 V
最小供电电压：2.7 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD宽度：7 mm
uPs/uCs/外围集成电路类型：MICROCONTROLLERBase Number Matches：1

MC56F82316VLHR 数据手册

 浏览型号MC56F82316VLHR的Datasheet PDF文件第2页浏览型号MC56F82316VLHR的Datasheet PDF文件第3页浏览型号MC56F82316VLHR的Datasheet PDF文件第4页浏览型号MC56F82316VLHR的Datasheet PDF文件第5页浏览型号MC56F82316VLHR的Datasheet PDF文件第6页浏览型号MC56F82316VLHR的Datasheet PDF文件第7页 
Document Number MC56F823XX  
Rev. 3.0, 09/2016  
NXP Semiconductors  
Data Sheet: Technical Data  
MC56F823XX  
MC56F823xx  
Supports MC56F82323VFM,  
MC56F82316VLF, MC56F82313VLC  
Features  
• Communication interfaces  
– Up to two high-speed queued SCI (QSCI) modules  
with LIN slave functionality  
– One queued SPI (QSPI) module  
– One I2C/SMBus port  
• This family of digital signal controllers (DSCs) is  
based on the 32-bit 56800EX core. On a single chip,  
each device combines the processing power of a DSP  
and the functionality of an MCU, with a flexible set of  
peripherals to support many target applications:  
– Industrial control  
• Timers  
– One 16-bit quad timer (1 x 4 16-bit timer)  
– Two Periodic Interval Timers (PITs)  
– Home appliances  
– Smart sensors  
– Wireless charging  
– Power distribution systems  
– Motor control (ACIM, BLDC, PMSM, SR, stepper)  
– Photovoltaic systems  
• Security and integrity  
– Cyclic Redundancy Check (CRC) generator  
– Windowed Computer operating properly (COP)  
watchdog  
– External Watchdog Monitor (EWM)  
– Circuit breaker  
– Medical device/equipment  
• Clocks  
– Instrumentation  
– Two on-chip relaxation oscillators: 8 MHz (400 kHz  
at standby mode) and 200 kHz  
– Crystal / resonator oscillator  
• DSC based on 32-bit 56800EX core  
– Up to 50 MIPS at 50 MHz core frequency  
– DSP and MCU functionality in a unified, C-efficient  
architecture  
• System  
– DMA controller  
– Integrated power-on reset (POR) and low-voltage  
interrupt (LVI) and brown-out reset module  
– Inter-module crossbar connection  
– JTAG/enhanced on-chip emulation (EOnCE) for  
unobtrusive, real-time debugging  
• On-chip memory  
– Up to 32 KB flash memory  
– Up to 6 KB data/program RAM  
– On-chip flash memory and RAM can be mapped  
into both program and data memory spaces  
• Operating characteristics  
• Analog  
– Single supply: 3.0 V to 3.6 V  
– 5 V–tolerant I/O (except for RESETB pin which is a  
3.3 V pin only)  
– Two high-speed, 5-channel, 12-bit ADCs with  
dynamic x1, x2, and x4 programmable amplifier  
– Three analog comparators with integrated 6-bit DAC  
references  
– Operation ambient temperature: -40°C to 105°C  
– Up to two 12-bit digital-to-analog converters (DAC)  
• 48-pin LQFP, 32-pin LQFP and 32-pin QFN packages  
• One FlexPWM module with up to 6 PWM outputs  
NXP reserves the right to change the production detail specifications as may be  
required to permit improvements in the design of its products.  
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 		This family of digital signal controllers (DSCs) is based on the 32-bit 56800EX core.
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