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MC54HC574AJ PDF预览

MC54HC574AJ

更新时间: 2024-10-14 22:40:03
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 总线驱动器总线收发器触发器逻辑集成电路
页数 文件大小 规格书
7页 171K
描述
Octal 3-State Noninverting D Flip-Flop

MC54HC574AJ 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP,
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.29
其他特性:BROADSIDE VERSION OF 374系列:HC/UH
JESD-30 代码:R-CDIP-T20JESD-609代码:e0
长度:24.515 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):48 ns认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

MC54HC574AJ 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
J SUFFIX  
CERAMIC PACKAGE  
CASE 732–03  
20  
20  
The MC54/74HC574A is identical in pinout to the LS574. The device  
inputs are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
Data meeting the setup time is clocked to the outputs with the rising edge  
of the Clock. The Output Enable input does not affect the states of the  
flip–flops, but when Output Enable is high, all device outputs are forced to  
the high–impedance state. Thus, data may be stored even when the outputs  
are not enabled.  
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
1
The HC574A is identical in function to the HCT374A but has the flip–flop  
inputs on the opposite side of the package from the outputs to facilitate PC  
board layout.  
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
1
The HC574A is the noninverting version of the HC564.  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 µA  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
ORDERING INFORMATION  
MC54HCXXXAJ  
MC74HCXXXAN  
Ceramic  
Plastic  
MC74HCXXXADW SOIC  
Chip Complexity: 266 FETs or 66.5 Equivalent Gates  
PIN ASSIGNMENT  
OUTPUT  
ENABLE  
1
20  
V
CC  
LOGIC DIAGRAM  
D0  
2
3
4
19  
18  
17  
Q0  
Q1  
Q2  
2
3
4
5
6
19  
18  
17  
16  
15  
D1  
D2  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
D3  
D4  
5
16  
15  
14  
13  
12  
11  
Q3  
NON–  
INVERTING  
OUTPUTS  
DATA  
INPUTS  
6
Q4  
D5  
7
Q5  
7
8
14  
13  
D6  
8
Q6  
D7  
9
Q7  
9
11  
1
12  
D7  
Q7  
GND  
10  
CLOCK  
CLOCK  
PIN 20 = V  
CC  
PIN 10 = GND  
OUTPUT ENABLE  
FUNCTION TABLE  
Inputs  
Clock  
Output  
Design Criteria  
Internal Gate Count*  
Value  
66.5  
1.5  
Units  
OE  
D
Q
L
L
L
H
L
X
X
H
ea  
ns  
L
No Change  
Z
L,H,  
X
Internal Gate Propagation Delay  
Internal Gate Power Dissipation  
Speed Power Product  
H
5.0  
µW  
pJ  
X = Don’t Care  
Z = High Impedance  
0.0075  
* Equivalent to a two–input NAND gate.  
3/97  
REV 7  
Motorola, Inc. 1997  

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