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MC54HC244AJ PDF预览

MC54HC244AJ

更新时间: 2024-11-14 00:01:07
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 总线驱动器总线收发器逻辑集成电路
页数 文件大小 规格书
8页 129K
描述
Octal 3-State Noninverting Buffer/Line Driver/Line Receiver

MC54HC244AJ 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP,
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.13
系列:HC/UHJESD-30 代码:R-CDIP-T20
JESD-609代码:e0长度:24.515 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):27 ns
认证状态:Not Qualified座面最大高度:5.08 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

MC54HC244AJ 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 732–03  
20  
20  
High–Performance Silicon–Gate CMOS  
1
The MC54/74HC244A is identical in pinout to the LS244. The device  
inputs are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
This octal noninverting buffer/line driver/line receiver is designed to be  
used with 3–state memory address drivers, clock drivers, and other  
bus–oriented systems. The device has noninverting outputs and two  
active–low output enables.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
1
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
20  
20  
1
The HC244A is similar in function to the HC240A and HC241A.  
SD SUFFIX  
SSOP PACKAGE  
CASE 940C–03  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
1
DT SUFFIX  
TSSOP PACKAGE  
CASE 948E–02  
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
1
ORDERING INFORMATION  
MC54HCXXXAJ  
MC74HCXXXAN  
MC74HCXXXADW  
MC74HCXXXASD  
MC74HCXXXADT  
Ceramic  
Plastic  
SOIC  
SSOP  
TSSOP  
Chip Complexity: 136 FETs or 34 Equivalent Gates  
LOGIC DIAGRAM  
2
18  
PIN ASSIGNMENT  
A1  
YA1  
ENABLE A  
1
20  
V
CC  
4
6
8
16  
14  
12  
A2  
A3  
A4  
YA2  
YA3  
YA4  
A1  
YB4  
A2  
2
3
4
19  
18  
17  
ENABLE B  
YA1  
B4  
YB3  
A3  
5
16  
15  
14  
13  
12  
11  
YA2  
B3  
DATA  
INPUTS  
NONINVERTING  
OUTPUTS  
6
11  
13  
9
7
B1  
B2  
B3  
B4  
YB1  
YB2  
YB3  
YB4  
YB2  
A4  
7
YA3  
B2  
8
YB1  
GND  
9
YA4  
B1  
15  
17  
5
3
10  
FUNCTION TABLE  
PIN 20 = V  
PIN 10 = GND  
Inputs  
Enable A,  
Enable B A, B  
Outputs  
CC  
1
ENABLE A  
ENABLE B  
OUTPUT  
ENABLES  
19  
YA, YB  
L
L
H
L
H
X
L
H
Z
Z = high impedance  
10/95  
Motorola, Inc. 1995  
REV 6  

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