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MC34VR5100A1EP PDF预览

MC34VR5100A1EP

更新时间: 2024-11-30 01:17:35
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
108页 2964K
描述
Multi-output DC/DC regulator for low-power LS1 communication processors

MC34VR5100A1EP 数据手册

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Document Number: VR5100  
Rev. 4.0, 2/2017  
NXP Semiconductors  
Data sheet: Advance Information  
Multi-output DC/DC regulator for  
low-power LS1 communication  
processors  
VR5100  
The VR5100 is a high performance, highly integrated, multi-output, DC/DC  
regulator solution, with integrated power MOSFETs, ideally suited for the LS1  
family of communications processors. Integrating three buck converters, six  
linear regulators, RTC supply and a coin-cell charger, the VR5100 can provide  
power for a complete system, including communications processors, memory,  
and system peripherals.  
POWER MANAGEMENT  
Features:  
• Three adjustable high efficiency buck regulators: 3.8 A, 1.25 A, 1.5 A  
• Selectable modes: PWM, PFM, APS  
EP SUFFIX  
98ASA00719D  
48 QFN 7.0 X 7.0  
• 5.0 V, 600 mA boost regulator with PFM or Auto mode  
• Six adjustable general purpose linear regulators  
• Input voltage range: 2.8 V to 4.5 V  
Applications:  
• Network attached storage (NAS)  
• Value IOT gateway  
• Mobile NAS  
• OTP (One Time Programmable) memory for device configuration  
• Programmable start-up sequence and timing  
• Selectable output voltage, frequency, soft start  
• I2C control  
• Industrial control  
• Home/Factory automation  
• Always ON RTC supply and Coin cell charger  
• DDR reference voltage  
• -40 °C to +125 °C operating junction temperature  
VR5100  
LS1012  
Main Supply  
2.8 – 4.5 V  
Switching regulators  
SW1  
VDDx  
0.7 to 1.425 V, 1.8V, 3.3V @ 3.8 A  
S1VDDx  
USB_SDVDD  
USB_SVDD  
XOSC_VDD  
SW2  
AVDD_CGA1  
AVDD_PLAT  
1.50 to 1.85 V @ 1.25 A  
or 2.5 to 3.3 V @ 1.25 A  
O1VDDx  
O2VDDx  
THVDD  
SW3  
G1_VDDx  
0.90 to 1.65 V @ 1.5 A  
AVDD_SD1_PLLx  
AVDD_REF  
SWBST  
5.00 to 5.15 V @ 0.6 A  
Linear regulators  
X1VDD_x  
DDR Memory  
REFOUT  
LICELL  
Charger  
COINCELL  
LDO1  
1.8 to 3.3 V @ 100 mA  
VCC_POVD  
LDO2  
0.80 to 1.55 V @ 250 mA  
LDO3  
1.8 - 3.3 V @ 100 mA  
LDO4  
1.8 - 3.3 V @ 350 mA  
V33  
USB_HVDD  
EVDD  
2.85 - 3.3 V @ 350 mA  
VSD  
1.8 V @ 100 mA  
or 3.3V @ 100 mA  
PORB  
EN  
STBY  
Parallel control/GPIOS  
I2C  
SD_VSEL  
INTB  
I2C  
Figure 1. VR5100 simplified application diagram  
* This document contains certain information on a new product.  
Specifications and information herein are subject to change without notice.  
© NXP Semiconductors N.V. 2017  

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