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MC34712EP PDF预览

MC34712EP

更新时间: 2024-04-09 18:59:33
品牌 Logo 应用领域
恩智浦 - NXP 双倍数据速率
页数 文件大小 规格书
29页 1072K
描述
Switch-Mode Power Supply, Fully Integrated DDR , 3.0 A 1.0 MHz, QFN 24

MC34712EP 数据手册

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Document Number: MC34712  
Rev. 8.0, 8/2016  
NXP Semiconductors  
Data Sheet: Technical Data  
3.0 A 1.0 MHz fully integrated DDR  
switch-mode power supply  
34712  
The SMARTMOS 34712 is a highly integrated, space efficient, low cost, single  
synchronous buck switching regulator with integrated N-channel power  
MOSFETs. It is a high performance point-of-load (PoL) power supply with the  
ability to track an external reference voltage.  
SWITCH-MODE POWER SUPPLY  
Its high efficient 3.0 A sink and source capability combined with its voltage  
tracking/sequencing ability and tight output regulation, makes it ideal to provide  
the termination voltage (VTT) for modern data buses such as Double-Data-Rate  
(DDR) memory buses, including but not limited to DDR, DDR2, DDR3, and  
DDR4 memories. It also provides a buffered output reference voltage (VREF) to  
the memory chipset  
The 34712 offers the designer the flexibility of many control, supervisory, and  
protection functions to allow for easy implementation of complex designs. It is  
housed in a Pb-free, thermally enhanced, and space efficient 24 pin exposed  
pad QFN.  
Features  
• 50 mΩ integrated N-channel power MOSFETs  
• Input voltage operating range from 3.0 V to 6.0 V  
EP SUFFIX  
98ARL10577D  
24-PIN QFN  
1% Accurate output voltage, ranging from 0.6 V to 1.35 V  
1% Accurate buffered reference output voltage  
• Programmable switching frequency range from 200 kHz to 1.0 MHz with a  
default of 1.0 MHz  
• Overcurrent limit and short-circuit protection  
• Thermal shutdown  
• Output overvoltage and undervoltage detection  
• Active low power-good output signal  
• Active low standby and shutdown inputs  
VIN  
(3.0 TO 6.0 V)  
34712  
PVIN  
BOOT  
TERMINATING  
RESISTORS  
VDDQ  
VREFIN  
VTT  
SW  
VOUT  
VIN  
MEMORY  
BUS  
VDDQ  
VDDI  
FREQ  
GND  
SD  
INV  
DDR MEMORY  
CHIPSET  
COMP  
VDDQ  
VREFOUT  
VREF  
VIN  
DDR MEMORY  
CONTROLLER  
PGND  
PG  
MCU  
STBY  
Figure 1. 34712 simplified application diagram  
© 2016 NXP B.V.  

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