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MC34085BDWR2 PDF预览

MC34085BDWR2

更新时间： 2024-11-24 14:53:11
品牌 Logo 应用领域
安森美 - ONSEMI 放大器光电二极管
页数 文件大小 规格书
16页 271K
描述
IC,OP-AMP,QUAD,BIPOLAR/JFET,SOP,16PIN,PLASTIC

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中文翻译

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MC34085BDWR2 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：SOP, SOP16,.4Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.33.00.01
风险等级：5.91放大器类型：OPERATIONAL AMPLIFIER
架构：VOLTAGE-FEEDBACK25C 时的最大偏置电流 (IIB)：0.0002 µA
频率补偿：YES (AVCL>=2)最大输入失调电压：14000 µV
JESD-30 代码：R-PDSO-G16JESD-609代码：e0
低-偏置：YES低-失调：NO
标称负供电电压 (Vsup)：-15 V功能数量：4
端子数量：16最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TAPE AND REEL电源：+-15 V
认证状态：Not Qualified最小摆率：35 V/us
子类别：Operational Amplifier最大压摆率：13 mA
供电电压上限：22 V标称供电电压 (Vsup)：15 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
最小电压增益：15000Base Number Matches：1

MC34085BDWR2 数据手册

 浏览型号MC34085BDWR2的Datasheet PDF文件第2页浏览型号MC34085BDWR2的Datasheet PDF文件第3页浏览型号MC34085BDWR2的Datasheet PDF文件第4页浏览型号MC34085BDWR2的Datasheet PDF文件第5页浏览型号MC34085BDWR2的Datasheet PDF文件第6页浏览型号MC34085BDWR2的Datasheet PDF文件第7页 
ON Semiconductort  
MC34080  
thru  
MC34085  
High Slew Rate, Wide  
Bandwidth, JFET Input  
Operational Amplifiers  
These devices are a new generation of high speed JFET input monolithic  
operational amplifiers. Innovative design concepts along with JFET  
technology provide wide gain bandwidth product and high slew rate.  
Well–matched JFET input devices and advanced trim techniques ensure low  
input offset errors and bias currents. The all NPN output stage features large  
output voltage swing, no deadband crossover distortion, high capacitive  
drive capability, excellent phase and gain margins, low open loop output  
impedance, and symmetrical source/sink AC frequency response.  
This series of devices is available in fully compensated or  
decompensated (AVCL≤2) and is specified over a commercial temperature  
range. They are pin compatible with existing Industry standard operational  
amplifiers, and allow the designer to easily upgrade the performance of  
existing designs.  
HIGH PERFORMANCE  
JFET INPUT  
OPERATIONAL AMPLIFIERS  
8
8
1
1
P SUFFIX  
PLASTIC PACKAGE  
CASE 626  
D SUFFIX  
PLASTIC PACKAGE  
CASE 751  
(SO–8)  
• Wide Gain Bandwidth: 8.0 MHz for Fully Compensated Devices  
Wide Gain Bandwidth: 16 MHz for Decompensated Devices  
PIN CONNECTIONS  
• High Slew Rate: 25 V/µs for Fully Compensated Devices  
High Slew Rate: 50 V/µs for Decompensated Devices  
1
2
3
4
8
Offset Null  
Inv. Input  
NC  
• High Input Impedance: 1012  
Ω
-
+
7
6
5
V
CC  
• Input Offset Voltage: 0.5 mV Maximum (Single Amplifier)  
Noninv. Input  
Output  
• Large Output Voltage Swing: –14.7 V to +14 V for  
V
EE  
Offset Null  
Large Output Voltage Swing: VCC/VEE = ±15 V  
(Single, Top View)  
• Low Open Loop Output Impedance: 30 Ω @ 1.0 MHz  
• Low THD Distortion: 0.01%  
1
2
3
4
8
7
6
5
V
Output 1  
Inputs 1  
CC  
• Excellent Phase/Gain Margins: 55°/7.6 dB for Fully Compensated  
Output 2  
–
+
Devices  
–
+
Inputs 2  
V
EE  
ORDERING INFORMATION  
Fully  
Compen-  
sated  
Operating  
Temperature  
Range  
(Dual, Top View)  
Op Amp  
Function  
A
≥2  
VCL  
Compensated  
MC34080BD  
MC34080BP  
MC34083BP  
Package  
SO–8  
MC34081BD  
MC34081BP  
MC34082P  
Single  
Dual  
Plastic DIP  
Plastic DIP  
SO–16L  
T = 0° to +70°C  
A
16  
14  
1
1
MC34084DW MC34085BDW  
Quad  
T = 0° to +70°C  
A
P SUFFIX  
DW SUFFIX  
PLASTIC PACKAGE  
CASE 751G  
MC34084P  
MC34085BP  
Plastic DIP  
PLASTIC PACKAGE  
CASE 646  
(SO–16L)  
PIN CONNECTIONS  
1
2
3
4
5
6
7
8
16  
Output 1  
Inputs 1  
Output 4  
Output 1  
Inputs 1  
1
2
3
4
14  
13  
12  
11  
10  
9
Output 4  
Inputs 4  
15  
-
+
-
+
-
+
Inputs 4  
-
+
14  
13  
12  
11  
10  
1
4
3
1
4
3
V
CC  
V
EE  
V
CC  
V
EE  
+
-
+
-
5
+
-
+
-
Inputs 2  
Inputs 3  
Inputs 2  
Output 2  
2
Inputs 3  
Output 3  
2
6
7
Output 2  
NC  
Output 3  
NC  
8
9
(Quad, Top View)  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
March, 2002 – Rev. 1  
MC34080/D  
1234567...16

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