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MC34081BDR2 PDF预览

MC34081BDR2

更新时间： 2024-11-20 15:40:59
品牌 Logo 应用领域
安森美 - ONSEMI 放大器光电二极管
页数 文件大小 规格书
16页 282K
描述
OP-AMP, 4000uV OFFSET-MAX, 8MHz BAND WIDTH, PDSO8, PLASTIC, SO-8

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中文翻译

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MC34081BDR2 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：PLASTIC, SO-8
针数：8Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.33.00.01
风险等级：5.75放大器类型：OPERATIONAL AMPLIFIER
架构：VOLTAGE-FEEDBACK最大平均偏置电流 (IIB)：0.004 µA
25C 时的最大偏置电流 (IIB)：0.0001 µA标称共模抑制比：90 dB
频率补偿：YES最大输入失调电压：4000 µV
JESD-30 代码：R-PDSO-G8JESD-609代码：e0
长度：4.9 mm低-偏置：YES
低-失调：NO负供电电压上限：-22 V
标称负供电电压 (Vsup)：-15 V功能数量：1
端子数量：8最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：+-15 V认证状态：Not Qualified
座面最大高度：1.75 mm最小摆率：20 V/us
标称压摆率：25 V/us子类别：Operational Amplifier
最大压摆率：4.2 mA供电电压上限：22 V
标称供电电压 (Vsup)：15 V表面贴装：YES
技术：BIPOLAR温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED标称均一增益带宽：8000 kHz
最小电压增益：25000宽度：3.9 mm
Base Number Matches：1

MC34081BDR2 数据手册

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Order this document by MC34080/D  
t
HIGH PERFORMANCE  
JFET INPUT  
OPERATIONAL AMPLIFIERS  
These devices are a new generation of high speed JFET input monolithic  
operational amplifiers. Innovative design concepts along with JFET  
technology provide wide gain bandwidth product and high slew rate.  
Well–matched JFET input devices and advanced trim techniques ensure low  
input offset errors and bias currents. The all NPN output stage features large  
output voltage swing, no deadband crossover distortion, high capacitive  
drive capability, excellent phase and gain margins, low open loop output  
impedance, and symmetrical source/sink AC frequency response.  
This series of devices is available in fully compensated or  
8
decompensated (A ≤2) and is specified over a commercial temperature  
VCL  
8
1
range. They are pin compatible with existing Industry standard operational  
amplifiers, and allow the designer to easily upgrade the performance of  
existing designs.  
1
P SUFFIX  
PLASTIC PACKAGE  
CASE 626  
D SUFFIX  
PLASTIC PACKAGE  
CASE 751  
• Wide Gain Bandwidth: 8.0 MHz for Fully Compensated Devices  
(SO–8)  
Wide Gain Bandwidth: 16 MHz for Decompensated Devices  
PIN CONNECTIONS  
• High Slew Rate: 25 V/µs for Fully Compensated Devices  
High Slew Rate: 50 V/µs for Decompensated Devices  
12  
1
2
3
4
8
Offset Null  
Inv. Input  
NC  
• High Input Impedance: 10  
Ω
–
+
7
6
5
V
• Input Offset Voltage: 0.5 mV Maximum (Single Amplifier)  
• Large Output Voltage Swing: –14.7 V to +14 V for  
CC  
Noninv. Input  
Output  
V
Offset Null  
Large Output Voltage Swing: V /V  
CC EE  
= ±15 V  
EE  
• Low Open Loop Output Impedance: 30 Ω @ 1.0 MHz  
• Low THD Distortion: 0.01%  
(Single, Top View)  
1
2
3
4
8
7
6
5
V
CC  
Output 2  
Output 1  
Inputs 1  
• Excellent Phase/Gain Margins: 55°/7.6 dB for Fully Compensated  
Devices  
–
+
–
+
Inputs 2  
V
EE  
ORDERING INFORMATION  
(Dual, Top View)  
Fully  
Compen-  
sated  
Operating  
Temperature  
Range  
Op Amp  
Function  
A
≥2  
VCL  
Compensated  
MC34080BD  
MC34080BP  
MC34083BP  
Package  
SO–8  
MC34081BD  
MC34081BP  
MC34082P  
Single  
Dual  
T
= 0° to +70°C  
T = 0° to +70°C  
A
Plastic DIP  
Plastic DIP  
SO–16L  
A
16  
14  
1
1
MC34084DW MC34085BDW  
Quad  
P SUFFIX  
DW SUFFIX  
MC34084P  
MC34085BP  
Plastic DIP  
PLASTIC PACKAGE  
CASE 646  
PLASTIC PACKAGE  
CASE 751G  
(SO–16L)  
PIN CONNECTIONS  
1
16  
Output 1  
Output 4  
Output 1  
Inputs 1  
1
2
3
4
14  
13  
12  
11  
10  
9
Output 4  
2
Inputs 1  
3
15  
–
–
+
–
+
Inputs 4  
–
+
+
Inputs 4  
14  
13  
12  
11  
10  
1
4
3
1
4
3
4
V
V
CC  
EE  
V
V
CC  
EE  
Inputs 3  
Output 3  
5
+
–
+
–
5
+
–
+
–
Inputs 2  
6
Inputs 3  
Inputs 2  
Output 2  
2
2
6
7
Output 2  
NC  
7
8
Output 3  
NC  
8
9
(Quad, Top View)  
Motorola, Inc. 1996  
Rev 0  
1234567...16

中文翻译

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