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MC14562BCP

更新时间: 2024-01-08 14:55:32
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
6页 187K
描述
128-Bit Static Shift Register

MC14562BCP 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP14,.3Reach Compliance Code:unknown
风险等级:5.92JESD-30 代码:R-XDIP-T14
JESD-609代码:e0位数:128
功能数量:1端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5/15 V
认证状态:Not Qualified筛选级别:MIL-STD-883 Class B (Modified)
子类别:Shift Registers表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

MC14562BCP 数据手册

 浏览型号MC14562BCP的Datasheet PDF文件第2页浏览型号MC14562BCP的Datasheet PDF文件第3页浏览型号MC14562BCP的Datasheet PDF文件第4页浏览型号MC14562BCP的Datasheet PDF文件第5页浏览型号MC14562BCP的Datasheet PDF文件第6页 
SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC  
CASE 632  
The MC14562B is a 128–bit static shift register constructed with MOS  
P–channel and N–channel enhancement mode devices in a single  
monolithic structure. Data is clocked in and out of the shift register on the  
positive edge of the clock input. Data outputs are available every 16 bits,  
from 16 through bit 128. This complementary MOS shift register is primarily  
used where low power dissipation and/or high noise immunity is desired.  
P SUFFIX  
PLASTIC  
CASE 646  
Diode Protection on All Inputs  
Fully Static Operation  
Cascadable to Provide Longer Shift Register Lengths  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Capable of Driving Two Low–power TTL Loads or One Low–power  
Schottky TTL Load Over the Rated Temperature Range  
D SUFFIX  
SOIC  
CASE 751A  
ORDERING INFORMATION  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
T
A
= – 55° to 125°C for all packages.  
V
DD  
– 0.5 to + 18.0  
V , V  
in out  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
I , I  
in out  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
BLOCK DIAGRAM  
P
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
D
Q16  
Q32  
Q48  
Q64  
10  
13  
9
T
stg  
– 65 to + 150  
260  
12  
DATA  
T
Lead Temperature (8–Second Soldering)  
C
L
1
* Maximum Ratings are those values beyond which damage to the device may occur.  
Temperature Derating:  
Q80  
Q96  
Q112  
Q128  
8
2
6
3
5
CLOCK  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
LOGIC DIAGRAM  
Pins 4 and 11  
not used.  
V
V
= PIN 14  
= PIN 7  
DD  
SS  
CLOCK  
5
DATA IN 12  
D Q  
C
D
C
Q
D Q  
C
D Q  
C
D
C
Q
D Q  
C
D
C
Q
D Q  
C
D
C
Q
D Q  
C
1
2
3
16  
17  
32  
33  
48  
49  
64  
10 Q16  
13 Q32  
D Q  
C
D
C
Q
D Q  
C
D
C
Q
D Q  
C
D Q  
C
D
C
Q
D Q  
C
65  
80  
81  
96  
97  
112  
113  
128  
9
1
Q48  
Q64  
8
2
Q80  
Q96  
6
3
Q112  
Q128  
REV 3  
1/94  
Motorola, Inc. 1995  

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