SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 620
The MC14529B analog data selector is a dual 4–channel or single
8–channel device depending on the input coding. The device is suitable for
digital as well as analog application, including various one–of–four and
one–of–eight data selector functions. Since the device has bidirectional
analog characteristics it can also be used as a dual binary to 1–of–4 or a
binary to 1–of–8 decoder.
P SUFFIX
PLASTIC
CASE 648
•
•
•
•
•
Data Paths Are Bidirectional
3–State Outputs
Linear “On” Resistance
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load over the Rated Temperature Range.
D SUFFIX
SOIC
CASE 751B
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
ORDERING INFORMATION
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
V
DD
– 0.5 to + 18.0
V , V
Input or Output Voltage (DC or Transient)
– 0.5 to V
DD
+ 0.5
V
in out
I , I
T
A
= – 55° to 125°C for all packages.
Input or Output Current (DC or Transient),
per Pin
± 10
mA
in out
P
Power Dissipation, per Package†
Storage Temperature
500
mW
C
D
BLOCK DIAGRAM
T
stg
– 65 to + 150
260
T
Lead Temperature (8–Second Soldering)
C
3–STATE OUTPUT ENABLE
STROBE X 1
L
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
6
A
7
2
3
B
TRUTH TABLE (X = Don’t Care)
X0
X1
9
Z
ST
ST
B
A
Z
W
X
Y
4
5
X2
X3
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
X0
X1
X2
X3
Y0
Y1
Y2
Y3
Dual 4–Channel Mode
2 Outputs
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
X0
X1
X2
X3
14
13
12
11
Y0
Y1
10
W
Single 8–Channel Mode
1 Output
(Z and W tied together)
Y2
Y3
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
Y0
Y1
Y2
Y3
STROBE Y 15
V
V
= PIN 16
= PIN 8
DD
SS
0
0
X
X
High
Impedance
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V and
in
V
out
should be constrained to the range V
SS
≤ (V or V ) ≤ V .
in out DD
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either V or V ). Unused outputs must be left open.
SS DD
REV 3
1/94
Motorola, Inc. 1995
MOTOROLA CMOS LOGIC DATA
MC14529B
1