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MC145146P2 PDF预览

MC145146P2

更新时间: 2024-11-30 22:34:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 信号电路锁相环或频率合成电路光电二极管输入元件
页数 文件大小 规格书
2页 59K
描述
4 BIT DATA BUS INPUT BUS INPUT PLL FREQUENCY SYNTHESIZER

MC145146P2 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.8Is Samacsys:N
其他特性:7-BIT AUXILIARY INPUT COUNTER模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZER
JESD-30 代码:R-PDIP-T20JESD-609代码:e0
长度:26.415 mm功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE认证状态:Not Qualified
座面最大高度:4.57 mm最大供电电压 (Vsup):9 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

MC145146P2 数据手册

 浏览型号MC145146P2的Datasheet PDF文件第2页 
Order this document  
by MC145146–2/D  
SEMICONDUCTOR TECHNICAL DATA  
P SUFFIX  
PLASTIC DIP  
CASE 738  
Interfaces with Dual–Modulus Prescalers  
20  
1
The MC145146–2 is programmed by a 4–bit input, with strobe and address  
lines. The device features consist of a reference oscillator, 12–bit program-  
mable reference divider, digital phase detector, 10–bit programmable divide–  
by–N counter, 7–bit divide–by–A counter, and the necessary latch circuitry for  
accepting the 4–bit input data.  
DW SUFFIX  
SOG PACKAGE  
CASE 751D  
20  
Operating Temperature Range: – 40 to 85°C  
Low Power Consumption Through the Use of CMOS Technology  
3.0 to 9.0 V Supply Range  
Programmable Reference Divider for Values Between 3 and 4095  
Dual–Modulus 4–Bit Data Bus Programming  
÷ N Range = 3 to 1023, ÷ A Range = 0 to 127  
“Linearized” Digital Phase Detector Enhances Transfer Function Linearity  
Two Error Signal Options:  
1
ORDERING INFORMATION  
MC145146P2  
Plastic DIP  
MC145146DW2 SOG Package  
PIN ASSIGNMENT  
Single–Ended (Three–State)  
Double–Ended  
D1  
D0  
1
2
20  
19  
D2  
D3  
f
3
4
18  
17  
f
R
in  
NOT RECOMMENDED FOR NEW DESIGNS;  
PRODUCT TO BE PHASED OUT.  
V
φ
R
SS  
Closest equivalents are the MC145152–2, MC145170–1,  
MC14519X series, and MC14520X series.  
PD  
V
5
6
16  
15  
φ
V
out  
f
DD  
V
OSC  
in  
7
14  
13  
12  
11  
MC  
LD  
ST  
A2  
OSC  
8
out  
BLOCK DIAGRAM  
A0  
9
A1  
10  
f
12–BIT  
L5  
÷R COUNTER  
OSC  
in  
R
OSC  
out  
L6  
L7  
LOCK  
LD  
DETECT  
D0  
D1  
D2  
PHASE  
PD  
D3  
A2  
A1  
A0  
out  
DETECTOR A  
LATCH  
CONTROL  
CIRCUITRY  
LATCHES  
f
V
ST  
φ
V
PHASE  
L2  
L3  
L4  
L0  
L1  
DETECTOR B  
φ
R
f
in  
10–BIT  
÷
N COUNTER  
7–BIT  
÷
A COUNTER  
MODULUS CONTROL (MC)  
CONTROL LOGIC  
REV 2  
1/98  
Motorola, Inc. 1998  

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